u-boot.git/drivers/timer, branch v2018.05-rc3 Unnamed repository; edit this file 'description' to name the repository. Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR 2018-04-27T18:54:48+00:00 Tom Rini trini@konsulko.com 2018-04-18T17:50:47+00:00 d024236e5a31a2b4b82cbcc98b31b8170fc88d28 We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com> 
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
rockchip: timer: add compatible strings for rk3188 and rk3288 2018-04-25T20:20:05+00:00 Philipp Tomsich philipp.tomsich@theobroma-systems.com 2018-04-25T12:07:06+00:00 e0e1d3f98c78926b7dcff19244377ae1c545bab5 The DM driver for ockchip timer blocks is also applicable to the RK3188 and RK3288 timer blocks: add 'rockchip,rk3188-timer' and 'rockchip,rk3288-timer' to its compatible list to support devices claiming compatibility with these. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 
The DM driver for ockchip timer blocks is also applicable to the
RK3188 and RK3288 timer blocks: add 'rockchip,rk3188-timer' and
'rockchip,rk3288-timer' to its compatible list to support devices
claiming compatibility with these.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
timer: stm32: Add timer support for STM32 SoCs family 2018-03-14T01:45:37+00:00 Patrice Chotard patrice.chotard@st.com 2018-02-07T09:44:45+00:00 5120a083e797aec3180fbda9ab845486da990909 This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> 
This timer driver is using GPT Timer (General Purpose Timer)
available on all STM32 SOCs family.
This driver can be used on STM32F4/F7 and H7 SoCs family

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
atcpit100: timer: Remove arch dependency. 2017-11-30T01:39:31+00:00 Rick Chen rick@andestech.com 2017-11-23T04:48:46+00:00 0f4a395f782a2801842492d5b365ed095a1e69ef ATCPIT100 is often used in AE3XX platform which is based on NDS32 architecture recently. But in the future Andestech will have AE250 platform which is embeded ATCPIT100 timer based on RISCV architecture. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
ATCPIT100 is often used in AE3XX platform which is
based on NDS32 architecture recently. But in the future
Andestech will have AE250 platform which is embeded
ATCPIT100 timer based on RISCV architecture.

Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
cosmetic: atcpit100_timer: Use device api to get platdata 2017-11-30T01:39:07+00:00 Rick Chen rickchen36@gmail.com 2017-11-28T01:14:20+00:00 c6c85dc87d2ca044458429cb2b61c0dcaea9b7d6 Use dev_get_platdata to get private platdata. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
Use dev_get_platdata to get private platdata.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
cosmetic: atcpit100_timer: Rename function name as atcpit100 2017-11-30T01:39:01+00:00 Rick Chen rickchen36@gmail.com 2017-11-23T02:15:20+00:00 033d408102d68950aaba0011d9e9a07d9fbcf955 Integrate function and struct name as atcpit100 will be more reasonable. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
Integrate function and struct name as atcpit100 will be
more reasonable.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
ae3xx: timer: Rename AE3XX to ATCPIT100 2017-11-30T01:38:54+00:00 Rick Chen rickchen36@gmail.com 2017-11-28T01:23:23+00:00 fa3e354b2bcc9b07c89d0be190dd0e75cf54d6c6 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
ATCPIT100 is Andestech timer IP which is embeded
in AE3XX and AE250 boards. So rename AE3XX to
ATCPIT100 will be more make sence.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
ae3xx: timer: Fix ae3xx timer work abnormal in 64 bit. 2017-11-30T01:38:21+00:00 Rick Chen rick@andestech.com 2017-11-23T03:04:34+00:00 0e920ef052e2a5d33b1fd37b0b0ef7b74831e851 It will be work fine with unsigned long declaretion in timer register struct when system is 32 bit. But it will not work well when system is 64 bit. Replace it by u32 and verify both ok in 32/64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
It will be work fine with unsigned long declaretion in timer
register struct when system is 32 bit. But it will not work
well when system is 64 bit. Replace it by u32 and verify both
ok in 32/64 bit.

Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
sti: fix STMicroelectronics copyright 2017-11-06T14:51:01+00:00 Patrice Chotard patrice.chotard@st.com 2017-10-23T07:53:57+00:00 fb48bc448cb72b8e009dc659a84f43dd1dedafdc Uniformize all STMicroelectronics copyrights headers for STi related code. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> 
Uniformize all STMicroelectronics copyrights headers for STi
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
rockchip: timer: update for 32/64bit-aware OF_PLATDATA 2017-09-18T18:40:37+00:00 Philipp Tomsich philipp.tomsich@theobroma-systems.com 2017-08-14T17:05:31+00:00 8158a848fa4d506d46a5193daf13367f3839022a With dtoc emitting fdt64_t for addresses (and region sizes), the array indices for accessing the reg[] array needs to be adjusted. This adjusts the Rockchip DM timer driver to correctly handle OF_PLATDATA given this new structure layout. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
With dtoc emitting fdt64_t for addresses (and region sizes), the array
indices for accessing the reg[] array needs to be adjusted.  This
adjusts the Rockchip DM timer driver to correctly handle OF_PLATDATA
given this new structure layout.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>