u-boot.git/drivers/timer, branch v2018.11-rc2 Unnamed repository; edit this file 'description' to name the repository. timer: Add MPC83xx timer driver 2018-09-18T06:01:18+00:00 Mario Six mario.six@gdsys.cc 2018-08-06T08:23:38+00:00 2c21749d7118b66b98cbab3f6301576726e06525 Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> 
Add a timer driver for the MPC83xx architecture.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
timer: Sort Makefile entries 2018-09-18T06:01:18+00:00 Mario Six mario.six@gdsys.cc 2018-08-06T08:23:37+00:00 d259f975d475ced7623eb5a8fdc6abe82f996afd Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> 
Makefile entries should be sorted.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
dm: omap-timer: Update clock rate only if not populated 2018-09-11T00:48:19+00:00 Lokesh Vutla lokeshvutla@ti.com 2018-08-16T12:56:55+00:00 84b4221cffa805ab525be9a2d580f40f6d9a0243 timer_pre_probe() tries to populate the clock rate from DT. omap timer driver tries to overwrite this value irrespective of the value populated fro DT. So update this value only when DT doesn't populate the clock rate. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> 
timer_pre_probe() tries to populate the clock rate from DT. omap
timer driver tries to overwrite this value irrespective of the value
populated fro DT. So update this value only when DT doesn't populate
the clock rate.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
dm: omap-timer: Use 64bit for counter values 2018-09-11T00:48:19+00:00 Lokesh Vutla lokeshvutla@ti.com 2018-08-16T12:56:54+00:00 3ee15a51809998dda6bb94eea85237eb9fe698f0 In order to handle counter overflows use 64 bit values for counter. Also load the initial value during probe. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> 
In order to handle counter overflows use 64 bit values for counter.
Also load the initial value during probe.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
timer: dw-apb: Add Designware APB timer driver 2018-08-24T10:05:20+00:00 Marek Vasut marex@denx.de 2018-08-18T13:58:32+00:00 66011a0883ffc03135cd2d3649478c812e4f1b28 Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> 
Add timer driver for the Designware APB Timer IP. This is present
for example on the Altera SoCFPGA chips.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
x86: tsc: Try hardware calibration first 2018-08-20T05:52:49+00:00 Bin Meng bmeng.cn@gmail.com 2018-08-10T09:39:36+00:00 165db7c426f1946376c3643fd635afd6b167e3ee At present if TSC frequency is provided in the device tree, it takes precedence over hardware calibration result. This swaps the order to try hardware calibration first and uses device tree as last resort. This can be helpful when a generic dts (eg: coreboot/efi payload) is supposed to work on as many hardware as possible, including emulators like QEMU where TSC hardware calibration sometimes fails. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> 
At present if TSC frequency is provided in the device tree, it takes
precedence over hardware calibration result. This swaps the order to
try hardware calibration first and uses device tree as last resort.

This can be helpful when a generic dts (eg: coreboot/efi payload) is
supposed to work on as many hardware as possible, including emulators
like QEMU where TSC hardware calibration sometimes fails.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
x86: timer: tsc: Allow specifying clock rate from device tree again 2018-07-02T01:23:28+00:00 Bin Meng bmeng.cn@gmail.com 2018-06-23T10:03:47+00:00 94e72a6bd994078674188bee2efb727a110a1cc6 With the introduction of early timer support in the TSC driver, the capability of getting clock rate from device tree was lost unfortunately. Now we bring such functionality back, but with a limitation that when TSC is used as early timer, specifying clock rate from device tree does not work. This fixes random boot failures seen on QEMU targets: printing "TSC frequency is ZERO" and reset forever. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
With the introduction of early timer support in the TSC driver,
the capability of getting clock rate from device tree was lost
unfortunately. Now we bring such functionality back, but with a
limitation that when TSC is used as early timer, specifying clock
rate from device tree does not work.

This fixes random boot failures seen on QEMU targets: printing "TSC
frequency is ZERO" and reset forever.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
timer: cadence: Implement timer_get_boot_us 2018-06-15T06:06:31+00:00 Michal Simek michal.simek@xilinx.com 2018-04-18T12:03:56+00:00 56c0e646c4f6aeb263d9bff01b3619d81a0b062e This function is required for adding bootstage support. Also enable it directly for ZynqMP R5 configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
This function is required for adding bootstage support.
Also enable it directly for ZynqMP R5 configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
x86: tsc: add support for reading CPU freq from cpuid 2018-06-13T01:50:57+00:00 Christian Gmeiner christian.gmeiner@gmail.com 2018-05-14T09:32:17+00:00 acc2482fd8079a062c051cfaac16054f527acab4 Starting with cpuid level 0x16 (Skylake-based processors) it is possible to get CPU base freq via cpuid. This fixes booting on a skylake based system. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed wrong indention of labels] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> 
Starting with cpuid level 0x16 (Skylake-based processors)
it is possible to get CPU base freq via cpuid.

This fixes booting on a skylake based system.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed wrong indention of labels]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
timer: cadence: Use live-tree functions 2018-05-31T11:50:39+00:00 Michal Simek michal.simek@xilinx.com 2018-05-16T08:56:09+00:00 72b88103bb9b6bf8f4e9864200bb1811e32f878c Use live-tree functions. Reported-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
Use live-tree functions.

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>