u-boot.git/drivers/timer, branch v2022.07 Unnamed repository; edit this file 'description' to name the repository. timer: npcm: Add NPCM timer support 2022-05-05T13:28:47+00:00 Jim Liu jim.t90615@gmail.com 2022-04-19T05:32:22+00:00 b789e4f215614e3aee2f78925683dc722ca617fc Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> 
Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
vpl: Add Kconfig options for VPL 2022-05-02T13:58:13+00:00 Simon Glass sjg@chromium.org 2022-04-30T06:56:53+00:00 747093dd4089bdb2eccae90d7bccf33198e78eaa Add VPL versions of commonly used Kconfig options. Signed-off-by: Simon Glass <sjg@chromium.org> 
Add VPL versions of commonly used Kconfig options.

Signed-off-by: Simon Glass <sjg@chromium.org>
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER 2022-04-26T06:54:41+00:00 Eugen Hristev eugen.hristev@microchip.com 2022-04-04T08:35:51+00:00 632422d4b333f3580b9fd28c424ff728ed3d3bad This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> 
This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 0.3 KBytes.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB 2022-04-26T06:53:49+00:00 Eugen Hristev eugen.hristev@microchip.com 2022-04-04T08:35:50+00:00 e135d2c2f385fc1cefcea64cf775c6f0267945a2 This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> 
This commit allows the ATMEL_TCB driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 1 KByte.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
nds32: Remove the architecture 2022-04-25T20:04:05+00:00 Tom Rini trini@konsulko.com 2022-04-06T13:21:25+00:00 11232139e399e70641410356ae6b278113d90f16 As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> 
As removal of nds32 has been ack'd for the Linux kernel, remove support
here as well.

Cc: Rick Chen <rick@andestech.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
rockchip: timer: dw-apb-timer: fix whitespace in U_BOOT_DRIVER structure 2022-04-18T03:25:13+00:00 Johan Jonker jbx6244@gmail.com 2022-04-09T16:55:07+00:00 3930209526b32d9075ee9c01e87ee50201934313 The line with .of_to_plat in the U_BOOT_DRIVER structure of dw-apb-timer.c is not aligned with the rest. Add an extra TAB to fix the whitespace. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
The line with .of_to_plat in the U_BOOT_DRIVER structure
of dw-apb-timer.c is not aligned with the rest.
Add an extra TAB to fix the whitespace.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip: timer: add OF_PLATDATA support for dw-apb-timer 2022-04-18T03:25:13+00:00 Johan Jonker jbx6244@gmail.com 2022-04-09T16:55:06+00:00 516e216a788f62d6638e69632d97bc5798d29f1c The Rockchip rk3066 SoC has 3 dw-apb-timer nodes. U-boot is compiled with OF_PLATDATA TPL/SPL options, so add OF_PLATDATA support for the dw-apb-timer. Also change driver name to be able to compile with U-boot scripts. No reset OF_PLATDATA support was added, because the rk3066 nodes don't need/have them. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
The Rockchip rk3066 SoC has 3 dw-apb-timer nodes.
U-boot is compiled with OF_PLATDATA TPL/SPL options,
so add OF_PLATDATA support for the dw-apb-timer.
Also change driver name to be able to compile with
U-boot scripts. No reset OF_PLATDATA support was added,
because the rk3066 nodes don't need/have them.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze 2022-04-05T15:27:39+00:00 Tom Rini trini@konsulko.com 2022-04-05T15:27:39+00:00 037ef53cf01c522073a0a930c84c3ca858f032e1 Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers 
Xilinx changes for v2022.07-rc1 v2

xilinx:
- Allow booting bigger kernels till 100MB

zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device

serial_zynq:
- Change fifo behavior in DEBUG mode

zynq_sdhci:
- Fix BASECLK setting calculation

clk_zynqmp:
- Add support for showing video clock

gpio:
- Update slg driver to handle DT flags

net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver

pwm:
- Add driver for cadence PWM

versal:
- Add support for reserved memory

firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations

include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers
timer: atmel_tcb_timer: add atmel_tcb driver 2022-04-01T12:42:46+00:00 Clément Léger clement.leger@bootlin.com 2022-03-31T08:55:06+00:00 70fb1ae9dd30b1dc6cf0c6ba585f822ef58106e5 Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> 
Add a driver for the timer counter block that can be found on sama5d2.
This driver will be used when booting under OP-TEE since the pit timer
which is part of the SYSC is secured. Channel 1 & 2 are configured to
be chained together which allows to have a 64bits counter.

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
timer: cadence: Add bind function to driver 2022-03-30T12:43:26+00:00 Michal Simek michal.simek@xilinx.com 2021-10-15T13:17:28+00:00 dcbdd24259beaff903e7ffffde646a3c5bd756ac When DT node has pwm-cells property it shouldn't be bind as timer driver but as PWM driver. That's why make sure that this property is checked. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/434ef195fbedea9f83672a12d1ace0da16e8832e.1634303847.git.michal.simek@xilinx.com 
When DT node has pwm-cells property it shouldn't be bind as timer driver
but as PWM driver. That's why make sure that this property is checked.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/434ef195fbedea9f83672a12d1ace0da16e8832e.1634303847.git.michal.simek@xilinx.com