u-boot.git/drivers/timer, branch v2023.01 Unnamed repository; edit this file 'description' to name the repository. timer: orion-timer: Fix problem with early static variable 2023-01-02T08:14:16+00:00 Stefan Roese sr@denx.de 2022-12-21T09:18:49+00:00 5387b093cb7914b3c0404da928fa4bafdffac291 We've noticed that at least one Kirkwood board (Pogo v4) has problems with the new orion DM timer implementation. Debugging revealed that this issue is related with the static variable "early_init_done" which does not work correctly before relocation in all cases. This patch removes this static variable and replaces it's functionality via a function that detects if the timer is already initialized. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pali Rohár <pali@kernel.org> Cc: Michael Walle <michael@walle.cc> Cc: Tony Dinh <mibodhi@gmail.com> Tested-by: Tony Dinh <mibodhi@gmail.com> 
We've noticed that at least one Kirkwood board (Pogo v4) has problems
with the new orion DM timer implementation. Debugging revealed that this
issue is related with the static variable "early_init_done" which does
not work correctly before relocation in all cases.

This patch removes this static variable and replaces it's functionality
via a function that detects if the timer is already initialized.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pali Rohár <pali@kernel.org>
Cc: Michael Walle <michael@walle.cc>
Cc: Tony Dinh <mibodhi@gmail.com>
Tested-by: Tony Dinh <mibodhi@gmail.com>
timer: xilinx-timer: use timer_conv_64() to fix timer wrap around 2022-11-22T14:02:07+00:00 Ovidiu Panait ovpanait@gmail.com 2022-10-12T05:36:56+00:00 b34bc22bd9921547246c117fb95eb58bedaceff5 Current xilinx_timer_get_count() implementation does not take into account the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter register value. The roll-overs cause problems in the upper timer layers, as generic timer code expects an incrementing 64-bit value from get_count() to work correctly. Add the missing 64-bit up-conversion to fix random hangs/delays in __udelay(). Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver") Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> 
Current xilinx_timer_get_count() implementation does not take into account
the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter
register value. The roll-overs cause problems in the upper timer layers, as
generic timer code expects an incrementing 64-bit value from get_count() to
work correctly.

Add the missing 64-bit up-conversion to fix random hangs/delays in
__udelay().

Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
timer-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOC 2022-11-22T14:02:07+00:00 Ovidiu Panait ovpanait@gmail.com 2022-10-12T05:36:55+00:00 8272d4cb897ca15eef2f39afe488f6731312e5c2 Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled. The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done logic works for drivers that use DM_FLAG_PRE_RELOC. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20221012053656.1492457-2-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> 
Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled.

The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done
logic works for drivers that use DM_FLAG_PRE_RELOC.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20221012053656.1492457-2-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
timer-uclass: add timer_get_ops() macro 2022-11-22T14:02:07+00:00 Ovidiu Panait ovpanait@gmail.com 2022-10-12T05:36:54+00:00 1e766a04c723e003c001c0f1a4f301aef026a75e Align timer uclass with the other subsystems and provide a timer_get_ops() convenience macro. Using this instead of the generic device_get_ops() also prevents -Wdiscarded-qualifiers warnings when used with non-const variables. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20221012053656.1492457-1-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> 
Align timer uclass with the other subsystems and provide a timer_get_ops()
convenience macro.

Using this instead of the generic device_get_ops() also prevents
-Wdiscarded-qualifiers warnings when used with non-const variables.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20221012053656.1492457-1-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Merge branch '2022-11-02-assorted-updates' 2022-11-03T12:29:10+00:00 Tom Rini trini@konsulko.com 2022-11-03T12:29:10+00:00 36bc9b6113ca96ca5c0d821195adede38395befd - Improve arm semihosting, NPCM8xx pinctrl driver, SP804 uclass timer driver (and enable on relevant platforms), pvblock cleanup, eeprom cmd bugfix, add RTI watchdog nodes to k3-am64-main, evb-ast2500 config updates. 
- Improve arm semihosting, NPCM8xx pinctrl driver, SP804 uclass timer
  driver (and enable on relevant platforms), pvblock cleanup, eeprom cmd
  bugfix, add RTI watchdog nodes to k3-am64-main, evb-ast2500 config
  updates.
riscv: Rename Andes PLIC to PLICSW 2022-11-03T05:27:56+00:00 Yu Chien Peter Lin peterlin@andestech.com 2022-10-25T15:03:50+00:00 a5dfa3b8a0f7ad555495bad1386613d2de4ba619 As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com> 
As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
timer: add SP804 UCLASS timer driver 2022-11-02T17:58:17+00:00 Andre Przywara andre.przywara@arm.com 2022-10-20T22:10:23+00:00 731d108dd0706e76addc6945e8c8709a05cb4728 The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down timer IP with interrupt functionality, and is used in some SoCs from various vendors. Add a simple DM compliant timer driver, to allow users of the SP804 to switch to DM_TIMER. This relies on the input clock to be accessible via the DM clock framework, which should be fine as we probably look at fixed-clock's here anyway. We re-program the control register in the probe() function, but keep the divider in place, in case this has been set to something on purpose before. The TRM for the timer IP can be found here: https://developer.arm.com/documentation/ddi0271/latest Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down
timer IP with interrupt functionality, and is used in some SoCs from
various vendors.

Add a simple DM compliant timer driver, to allow users of the SP804 to
switch to DM_TIMER.

This relies on the input clock to be accessible via the DM clock
framework, which should be fine as we probably look at fixed-clock's
here anyway.
We re-program the control register in the probe() function, but keep
the divider in place, in case this has been set to something on purpose
before.

The TRM for the timer IP can be found here:
https://developer.arm.com/documentation/ddi0271/latest

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
timer: sti: convert sti-timer to arm a9 global timer 2022-10-31T12:55:59+00:00 William Zhang william.zhang@broadcom.com 2022-08-24T04:44:32+00:00 35751c7f3f01a6123e2965ad1b71a8e6a7a9c90d STI timer is actually ARM Cortex A9 global timer. Convert the driver to use generic global timer name and make it consistent with Linux kernel global timer driver. This also allows any A9 based device to use this driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> 
STI timer is actually ARM Cortex A9 global timer. Convert the driver to
use generic global timer name and make it consistent with Linux kernel
global timer driver. This also allows any A9 based device to use this
driver.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
timer: orion-timer: Only init timer once 2022-10-06T08:15:35+00:00 Stefan Roese sr@denx.de 2022-09-21T06:26:42+00:00 37bb396669b27aa62fe8bc5eeb6bfde92e09c2d3 Move the code making sure that the timer is initialized only once into orion_timer_init(), which is called from timer_early_init() and from orion_timer_probe(). This way the timer is not re-initialized. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Michael Walle <michael@walle.cc> Cc: Pali Rohár <pali@kernel.org> 
Move the code making sure that the timer is initialized only once into
orion_timer_init(), which is called from timer_early_init() and from
orion_timer_probe(). This way the timer is not re-initialized.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Michael Walle <michael@walle.cc>
Cc: Pali Rohár <pali@kernel.org>
timer: mtk: add support for MediaTek MT7981/MT7986 SoCs 2022-09-23T19:09:15+00:00 Weijie Gao weijie.gao@mediatek.com 2022-09-09T11:59:41+00:00 980e107d0f353a24cd4dcf3466cea068ec5e2eed This patch add general-purpose timer support for MediaTek MT7981/MT7986. These two SoCs uses a newer version of timer with its register definition slightly changed. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 
This patch add general-purpose timer support for MediaTek MT7981/MT7986.
These two SoCs uses a newer version of timer with its register definition
slightly changed.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>