u-boot.git/drivers/timer, branch v2023.10

riscv: allow riscv timer to be instantiated via device tree

2023-09-05T02:53:36+00:00

For the architectural timer on riscv, there already is a defined
device tree binding[1]. Allow timer instances to be created from
device tree matches, but for now retain the old mechanism, which
registers the timer biggy-back with the CPU.

[1] linux/Documentation/devicetree/bindings/timer/riscv,timer.yaml

Signed-off-by: Torsten Duwe 
Reviewed-by: Leo Yu-Chi Liang

omap: timer: add ti,am654-timer compatibility

2023-07-28T14:10:29+00:00

The TI AM654 timer is compatible with the omap-timer implementation,
so add it to the compatible id list.

Signed-off-by: Sjoerd Simons 
Reviewed-by: Roger Quadros 
Reviewed-by: Tom Rini 
Tested-by: Maxime Ripard 
Tested-by: Ravi Gunasekaran 
Tested-by: Mattijs Korpershoek 
Cc: Francesco Dolcini 
Cc: Wadim Egorov 
Signed-off-by: Nishanth Menon

riscv: Rename SiFive CLINT to RISC-V ALINT

2023-07-12T05:21:40+00:00

As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.

Signed-off-by: Bin Meng 
Reviewed-by: Rick Chen

riscv: timer: Update the sifive clint timer driver to support aclint

2023-07-12T05:21:40+00:00

This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.

The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.

[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Bin Meng 
Reviewed-by: Rick Chen

rockchip: timer: dw-apb-timer: use regs variable with uintptr_t size

2023-05-06T09:28:18+00:00

The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a regs variable with uintptr_t size in the
dw-apb-timer.c file.

Signed-off-by: Johan Jonker 
Reviewed-by: Simon Glass

Merge branch 'master' into next

2023-03-27T19:19:57+00:00

rockchip: timer: rockchip_timer: fix compatible and driver name

2023-03-19T06:12:01+00:00

In the binding for the Rockchip timer the compatible string
consists of a SoC orientated string and a fall back string
"rockchip,rk3288-timer", so remove all unneeded ones and
fix driver name.

Signed-off-by: Johan Jonker 
Reviewed-by: Kever Yang

Merge tag 'v2023.04-rc4' into next

2023-03-14T16:06:35+00:00

Prepare v2023.04-rc4

Signed-off-by: Tom Rini

efi: Use a fixed value for the timer clock

2023-03-13T12:53:01+00:00

It is not yet clear how to read the timer via EFI. The current value seems
much too high on a Framework laptop I tried. Adjust it to a lower
hard-coded value for now.

Signed-off-by: Simon Glass

timer: fttmr010: return a previously deleted driver now ported to DM

2023-03-06T22:03:56+00:00

The fttmr010 timer driver was deleted by
commit 29fc6f24926e ("ARM: remove a320evb board support")
The original source file was: arch/arm/cpu/arm920t/a320/timer.c

Return the driver to the codebase in a DM compatible form.
A platform using fttmr010 will be submitted later.

This hardware is described in the datasheet [1], starting from page 348.
According to the datasheet, there is a Revision Register at offset 0x3C,
which is not present in 'struct fttmr010'. Add it and debug() print
revision in probe function.

[1]
https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf

Signed-off-by: Sergei Antonov