u-boot.git/drivers/timer, branch v2024.01

riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode

2023-10-04T10:23:54+00:00

The Andes PLMT driver directly accesses the mtime MMIO region,
indicating its intended use in the M-mode boot stage. However,
since U-Boot proper (S-mode) also uses the PLMT driver, we need
to specifically mark the region as readable through PMPCFGx (or
S/U-mode read-only shared data region for Smepmp) in OpenSBI.

Granting permission for this case doesn't make sense. Instead,
we should use the generic RISC-V timer driver to read the mtime
through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER
config, which ensures that the PLMT driver is linked exclusively
against M-mode U-Boot or U-Boot SPL binaries.

Signed-off-by: Yu Chien Peter Lin 
Reviewed-by: Samuel Holland

timer: starfive: Add Starfive timer support

2023-10-04T09:59:31+00:00

Add timer driver in Starfive SoC. It is an timer that outside
of CPU core and inside Starfive SoC.

Signed-off-by: Kuan Lim Lee 
Reviewed-by: Wei Liang Lim 
Reviewed-by: Simon Glass

timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

2023-10-04T09:55:37+00:00

timer_get_boot_us function is required to record the boot stages as
us-based timestamp.
To get a micro-second time from a timer tick, this converts the
formula like below to avoid zero result of (tick / rate) part.

From: time(us) = (tick / rate) * 1000000
To  : time(us) = (tick * 1000) / (rate / 1000)

Signed-off-by: Chanho Park 
Reviewed-by: Leo Yu-Chi Liang

riscv: timer: add timer_get_boot_us for BOOTSTAGE

2023-10-04T09:55:20+00:00

timer_get_boot_us function is required to record the boot stages as
us-based timestamp.
To get a micro-second time from a timer tick, this converts the
formula like below to avoid zero result of (tick / rate) part.

From: time(us) = (tick / rate) * 1000000
To  : time(us) = (tick * 1000) / (rate / 1000)

Signed-off-by: Chanho Park 
Reviewed-by: Leo Yu-Chi Liang

Merge branch 'next'

2023-10-02T14:55:44+00:00

Signed-off-by: Tom Rini

timer: Remove unused NEEDS_MANUAL_RELOC code bits

2023-09-14T14:42:25+00:00

The last user of the NEEDS_MANUAL_RELOC has been removed in commit
26af162ac8f8 ("arch: m68k: Implement relocation")
Remove now unused NEEDS_MANUAL_RELOC code.

Signed-off-by: Marek Vasut

riscv: allow riscv timer to be instantiated via device tree

2023-09-05T02:53:36+00:00

For the architectural timer on riscv, there already is a defined
device tree binding[1]. Allow timer instances to be created from
device tree matches, but for now retain the old mechanism, which
registers the timer biggy-back with the CPU.

[1] linux/Documentation/devicetree/bindings/timer/riscv,timer.yaml

Signed-off-by: Torsten Duwe 
Reviewed-by: Leo Yu-Chi Liang

omap: timer: add ti,am654-timer compatibility

2023-07-28T14:10:29+00:00

The TI AM654 timer is compatible with the omap-timer implementation,
so add it to the compatible id list.

Signed-off-by: Sjoerd Simons 
Reviewed-by: Roger Quadros 
Reviewed-by: Tom Rini 
Tested-by: Maxime Ripard 
Tested-by: Ravi Gunasekaran 
Tested-by: Mattijs Korpershoek 
Cc: Francesco Dolcini 
Cc: Wadim Egorov 
Signed-off-by: Nishanth Menon

riscv: Rename SiFive CLINT to RISC-V ALINT

2023-07-12T05:21:40+00:00

As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.

Signed-off-by: Bin Meng 
Reviewed-by: Rick Chen

riscv: timer: Update the sifive clint timer driver to support aclint

2023-07-12T05:21:40+00:00

This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.

The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.

[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Bin Meng 
Reviewed-by: Rick Chen