u-boot.git/drivers/timer, branch v2025.10-rc2 Unnamed repository; edit this file 'description' to name the repository. Kbuild: Always use $(PHASE_) 2025-04-11T18:16:44+00:00 Tom Rini trini@konsulko.com 2025-04-01T22:55:23+00:00 302b41d5397e9f821d360a74335e8821d4513970 It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our Makefiles as part of the macros to determine when to do something in our Makefiles based on what phase of the build we are in. For consistency, bring this down to a single macro and use "$(PHASE_)" only. Signed-off-by: Tom Rini <trini@konsulko.com> 
It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.

Signed-off-by: Tom Rini <trini@konsulko.com>
test: Keep track of suite duration 2025-02-12T02:10:58+00:00 Simon Glass sjg@chromium.org 2025-02-07T18:30:35+00:00 5f6a59e03eff0f29295ce12b3807cbac7334e0aa Show the time taken by each test suite with 'ut all' and the total time for all suites. Take care to remove any sandbox time-offset from the values. Fix the comment-format on timer_test_add_offset() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> 
Show the time taken by each test suite with 'ut all' and the total time
for all suites.

Take care to remove any sandbox time-offset from the values.

Fix the comment-format on timer_test_add_offset() while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
powerpc: mpc83xx: Fix timer value calculation 2024-12-30T21:55:27+00:00 J. Neuschäfer j.ne@posteo.net 2024-12-20T10:37:51+00:00 deb26b6c29670dee743dfb54b8f69866339580bd TBU and TBL are specified as two 32-bit registers that form a 64-bit value, but the calculation only shifted TBU by 16 bits. Fix this by actually shifting 32 bits. Reviewed-by: Sinan Akman <sinan@writeme.com> Signed-off-by: J. Neuschäfer <j.ne@posteo.net> 
TBU and TBL are specified as two 32-bit registers that form a 64-bit
value, but the calculation only shifted TBU by 16 bits.

Fix this by actually shifting 32 bits.

Reviewed-by: Sinan Akman <sinan@writeme.com>
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
x86: Sync up tsc_timer with Linux 2024-10-18T20:10:21+00:00 Simon Glass sjg@chromium.org 2024-08-28T01:44:27+00:00 ecf31113f17817f5ab9263937270255b6d05cdf9 Since we are using the code from Linux, update it to the newer version in v6.11 Signed-off-by: Simon Glass <sjg@chromium.org> 
Since we are using the code from Linux, update it to the newer version
in v6.11

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Avoid timer-clock overflow 2024-10-18T20:10:21+00:00 Simon Glass sjg@chromium.org 2024-08-28T01:44:26+00:00 7c0f70b65b7c6ab0c09f87932615c65142542ed5 When the clock speed is above about 4GHz, e.g. on modern PC hardware, the timer overflows, resulting in a much lower frequency than expected. Deal with this by capping the clock speed. It would be possible to move to a 64-bit value for the clock, but that is a pain to deal with. A better approach might be to express the clock in MHz but that is left for later consideration. Signed-off-by: Simon Glass <sjg@chromium.org> 
When the clock speed is above about 4GHz, e.g. on modern PC hardware,
the timer overflows, resulting in a much lower frequency than expected.
Deal with this by capping the clock speed.

It would be possible to move to a 64-bit value for the clock, but that
is a pain to deal with. A better approach might be to express the clock
in MHz but that is left for later consideration.

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Ensure the CPU identity exists for timer init 2024-10-18T20:10:21+00:00 Simon Glass sjg@chromium.org 2024-08-28T01:44:25+00:00 3b2e4f542e3ea5d116d5830f4eef9be97d872312 When bootstage is used the timer can be inited before the CPU identity is set up, resulting in the checks for the vendor not working. Add a special call to work around this. Signed-off-by: Simon Glass <sjg@chromium.org> 
When bootstage is used the timer can be inited before the CPU identity
is set up, resulting in the checks for the vendor not working.

Add a special call to work around this.

Signed-off-by: Simon Glass <sjg@chromium.org>
global: Rename SPL_ to XPL_ 2024-10-11T17:44:48+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:53+00:00 c46760d5967d12b6f7d37402878d1607a98b2b84 Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is no-longer set. Signed-off-by: Simon Glass <sjg@chromium.org> 
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is
no-longer set.

Signed-off-by: Simon Glass <sjg@chromium.org>
timer: Add AST2700 IBEX timer support 2024-09-11T12:35:03+00:00 Chia-Wei Wang chiawei_wang@aspeedtech.com 2024-09-10T09:39:17+00:00 4b0129e8103dab9887d495d9c4dface8eeefb10b Add the driver for the AST2700 Ibex timer, which uses CPU cycles as the timer count running at 200MHz. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Add the driver for the AST2700 Ibex timer, which uses CPU
cycles as the timer count running at 200MHz.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
timer: npcm: Change counter source 2024-08-27T21:37:18+00:00 Jim Liu jim.t90615@gmail.com 2024-07-29T09:04:06+00:00 b70865e6b94fe81ddc4eb48f45b574eae80ee035 The counter value read from TDR register may not be correct. Read SECCNT and CNTR25M instead to get the correct timestamp. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> 
The counter value read from TDR register may not be correct.
Read SECCNT and CNTR25M instead to get the correct timestamp.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
drivers: timer: Remove duplicate newlines 2024-07-22T16:53:06+00:00 Marek Vasut marek.vasut+renesas@mailbox.org 2024-07-20T12:41:01+00:00 6478e02b2a5734d22e0137139eb30964a7a57798 Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> 
Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>