<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/usb/dwc3/core.c, branch v2020.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/usb/dwc3/core.c?h=v2020.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/usb/dwc3/core.c?h=v2020.07'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2020-05-29T10:13:19Z</updated>
<entry>
<title>usb: dwc3: amend UTMI/UTMIW phy interface setup</title>
<updated>2020-05-29T10:13:19Z</updated>
<author>
<name>Frank Wang</name>
<email>frank.wang@rock-chips.com</email>
</author>
<published>2020-05-26T03:34:30Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=646979425a9bbf23990b72098c9f70e45743f46a'/>
<id>urn:sha1:646979425a9bbf23990b72098c9f70e45743f46a</id>
<content type='text'>
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.

Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: Enable AutoRetry feature in the controller</title>
<updated>2020-05-29T10:13:19Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-05-26T03:34:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fafaa02290715a02ae97b26fa6937d6a27cdc296'/>
<id>urn:sha1:fafaa02290715a02ae97b26fa6937d6a27cdc296</id>
<content type='text'>
By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).

Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such transaction errors. That is, ACK TP
with Retry=1 and Nump != 0.

Doing so will give controller a chance to recover from transient error
conditions.

Reference from below Linux commit,

commit &lt;b138e23d3dff&gt; ("usb: dwc3: core: Enable AutoRetry feature
in the controller")

Cc: Marek Vasut &lt;marex@denx.de&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: Add disable u2mac linestate check quirk</title>
<updated>2020-05-29T10:13:19Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-05-26T03:33:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dc18413adbf188ffdfb0706023249e7c03b29545'/>
<id>urn:sha1:dc18413adbf188ffdfb0706023249e7c03b29545</id>
<content type='text'>
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.

When use this quirk, the controller implements a fixed 40-bit
TxEndDelay after the packet is given on UTMI and ignores the
linestate during the transmit of a token (during token-to-token
and token-to-data IPGAP).

On some rockchip platforms (e.g. rk3399), it requires to disable
the u2mac linestate check to decrease the SSPLIT token to SETUP
token inter-packet delay from 566ns to 466ns, and fix the issue
that FS/LS devices not recognized if inserted through USB 3.0 HUB.

Reference from below Linux commit,

commit &lt;65db7a0c9816&gt; ("usb: dwc3: add disable u2mac linestate
check quirk")

Cc: Marek Vasut &lt;marex@denx.de&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: add dis_u2_freeclk_exists_quirk</title>
<updated>2020-05-29T10:13:19Z</updated>
<author>
<name>Frank Wang</name>
<email>frank.wang@rock-chips.com</email>
</author>
<published>2020-05-26T03:33:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b34f8b5de0fea945c2683e9e64d941c121aa02ad'/>
<id>urn:sha1:b34f8b5de0fea945c2683e9e64d941c121aa02ad</id>
<content type='text'>
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.

Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk")
in Linux Rockchip Kernel.

Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Tested-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: add dis_enblslpm_quirk</title>
<updated>2020-05-29T10:13:19Z</updated>
<author>
<name>Frank Wang</name>
<email>frank.wang@rock-chips.com</email>
</author>
<published>2020-05-26T03:33:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7bb62708397d93d92804749b4c4c8d796df418de'/>
<id>urn:sha1:7bb62708397d93d92804749b4c4c8d796df418de</id>
<content type='text'>
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.

Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.

Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Tested-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>common: Drop linux/delay.h from common header</title>
<updated>2020-05-19T01:19:23Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c05ed00afb95fa5237f16962fccf5810437317bf'/>
<id>urn:sha1:c05ed00afb95fa5237f16962fccf5810437317bf</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common: Drop linux/bug.h from common header</title>
<updated>2020-05-19T01:19:23Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=eb41d8a1befc45a30ccdab68fa3e099528486ffe'/>
<id>urn:sha1:eb41d8a1befc45a30ccdab68fa3e099528486ffe</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: add dis_del_phy_power_chg_quirk</title>
<updated>2020-05-12T07:27:14Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-05-06T07:50:25Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=73ca0140e124fddd2f12535215a4e5a6f4339c6f'/>
<id>urn:sha1:73ca0140e124fddd2f12535215a4e5a6f4339c6f</id>
<content type='text'>
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.

Reference from below Linux commit,

commit &lt;00fe081dc3a3&gt; ("usb: dwc3: add dis_del_phy_power_chg_quirk")

Cc: Marek Vasut &lt;marex@denx.de&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: use the phy bulk API to get phys</title>
<updated>2020-05-02T10:32:28Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2020-05-02T09:35:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6dfb8a8052ee024fd20150b558477ab5c3e6f0f9'/>
<id>urn:sha1:6dfb8a8052ee024fd20150b558477ab5c3e6f0f9</id>
<content type='text'>
Get a group of phys by the phy bulk API

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Signed-off-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
Reviewed-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>dma-mapping: move dma_map_(un)single() to &lt;linux/dma-mapping.h&gt;</title>
<updated>2020-02-19T13:27:30Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2020-02-14T07:40:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9d86b89c590832c9bcb1c69d5ccdecdf731f97ae'/>
<id>urn:sha1:9d86b89c590832c9bcb1c69d5ccdecdf731f97ae</id>
<content type='text'>
The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.

Factor them out to &lt;linux/dma-mapping.h&gt;, and make all drivers to
include &lt;linux/dma-mapping.h&gt; instead of &lt;asm/dma-mapping.h&gt;.

If we need to differentiate them for some architectures, we can
move the generic definitions to &lt;asm-generic/dma-mapping.h&gt;.

Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
</feed>
