<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/usb/dwc3, branch v2023.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/usb/dwc3?h=v2023.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/usb/dwc3?h=v2023.01'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2022-11-27T14:34:56Z</updated>
<entry>
<title>usb: dwc3: Drop support for "snps, ref-clock-period-ns" DT property</title>
<updated>2022-11-27T14:34:56Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2022-11-27T14:31:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=db5bace4f6cb37251a5863efe4c0c1547d1334bd'/>
<id>urn:sha1:db5bace4f6cb37251a5863efe4c0c1547d1334bd</id>
<content type='text'>
Drop support for quickly deprecated DT property "snps,ref-clock-period-ns"
to prevent its proliferation.

Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: Program GFLADJ</title>
<updated>2022-11-27T14:34:56Z</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@seco.com</email>
</author>
<published>2022-11-27T14:31:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c55ac51a550c8d2f8485abe94cb80c15b81d08fa'/>
<id>urn:sha1:c55ac51a550c8d2f8485abe94cb80c15b81d08fa</id>
<content type='text'>
GUCTL.REFCLKPER can only account for clock frequencies with integer
periods. To address this, program REFCLK_FLADJ with the relative error
caused by period truncation. The formula given in the register reference
has been rearranged to allow calculation based on rate (instead of
period), and to allow for fixed-point arithmetic.

Additionally, calculate a value for 240MHZDECR. This configures a
simulated 240Mhz clock using a counter with one fractional bit (PLS1).

This register is programmed only for versions &gt;= 2.50a, since this is
the check also used by commit db2be4e9e30c ("usb: dwc3: Add frame length
adjustment quirk").

[ marek: Ported from Linux kernel commit
         596c87856e08d ("usb: dwc3: Program GFLADJ") ]

Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
Signed-off-by: Marek Vasut &lt;marex@denx.de&gt; # Port from Linux
</content>
</entry>
<entry>
<title>usb: dwc3: Calculate REFCLKPER based on reference clock</title>
<updated>2022-11-27T14:34:56Z</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@seco.com</email>
</author>
<published>2022-11-27T14:31:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6bae0eb5b8bd7f7f87c7bf106acea869da187b66'/>
<id>urn:sha1:6bae0eb5b8bd7f7f87c7bf106acea869da187b66</id>
<content type='text'>
Instead of using a special property to determine the reference clock
period, use the rate of the reference clock. When we have a legacy
snps,ref-clock-period-ns property and no reference clock, use it
instead. Fractional clocks are not currently supported, and will be
dealt with in the next commit.

[ marek: Ported from Linux kernel commit
         5114c3ee24875 ("usb: dwc3: Calculate REFCLKPER based on reference clock") ]

Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
Signed-off-by: Marek Vasut &lt;marex@denx.de&gt; # Port from Linux
</content>
</entry>
<entry>
<title>usb: dwc3: reference clock period configuration</title>
<updated>2022-11-27T14:34:56Z</updated>
<author>
<name>Balaji Prakash J</name>
<email>bjagadee@codeaurora.org</email>
</author>
<published>2022-11-27T14:31:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=57548e8bc7cb6eb1c1a0206579c2a84737a70650'/>
<id>urn:sha1:57548e8bc7cb6eb1c1a0206579c2a84737a70650</id>
<content type='text'>
Set reference clock period when it differs from dwc3 default hardware
set.

We could calculate clock period based on reference clock frequency. But
this information is not always available. This is the case of PCI bus
attached USB host. For that reason we use a custom property.

Tested (USB2 only) on IPQ6010 SoC based board with 24 MHz reference
clock while hardware default is 19.2 MHz.

[ baruch: rewrite commit message; drop GFLADJ code; remove 'quirk-' from
  property name; mention tested hardware ]

[ marek: Ported from Linux kernel commit
         7bee318838890 ("usb: dwc3: reference clock period configuration") ]

Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Signed-off-by: Balaji Prakash J &lt;bjagadee@codeaurora.org&gt;
Signed-off-by: Baruch Siach &lt;baruch@tkos.co.il&gt;
Signed-off-by: Marek Vasut &lt;marex@denx.de&gt; # Port from Linux
</content>
</entry>
<entry>
<title>usb: dwc3: Cache ref_clk pointer in struct dwc3</title>
<updated>2022-11-27T14:34:56Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2022-11-27T14:31:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8ae84e64530e81f23066d86417b9225388ba96ae'/>
<id>urn:sha1:8ae84e64530e81f23066d86417b9225388ba96ae</id>
<content type='text'>
Cache ref_clk clock pointer in struct dwc3 . This is a preparatory
patch for subsequent backports from Linux kernel which configure
GFLADJ register content based on the ref_clk rate and therefore need
access to the ref_clk pointer.

It is possible to extract the clock pointer from existing clk_bulk
list of already claimed clock, no need to call clk_get*() again.

Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver</title>
<updated>2022-07-15T12:10:39Z</updated>
<author>
<name>Angus Ainslie</name>
<email>angus@akkea.ca</email>
</author>
<published>2022-07-14T15:11:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=582ce23c7870b93e361083b1578ae45ed61df9b6'/>
<id>urn:sha1:582ce23c7870b93e361083b1578ae45ed61df9b6</id>
<content type='text'>
Suppress warnings when building the SPL without USB_DWC3_GENERIC

Signed-off-by: Angus Ainslie &lt;angus@akkea.ca&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: Add support to reset usb ULPI phy</title>
<updated>2022-07-12T19:59:54Z</updated>
<author>
<name>T Karthik Reddy</name>
<email>t.karthik.reddy@xilinx.com</email>
</author>
<published>2022-07-08T09:21:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b252d79b0936d60b0c6c69e71b0233e58f9c961e'/>
<id>urn:sha1:b252d79b0936d60b0c6c69e71b0233e58f9c961e</id>
<content type='text'>
When usb PHY initialization is done, the PHY need to be reset.

Signed-off-by: T Karthik Reddy &lt;t.karthik.reddy@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: Fix non-usb3 configurations</title>
<updated>2022-05-20T21:30:36Z</updated>
<author>
<name>Jan Kiszka</name>
<email>jan.kiszka@siemens.com</email>
</author>
<published>2022-04-25T11:26:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=868d58f69c7ceda5c886293cf15f4e39493517a2'/>
<id>urn:sha1:868d58f69c7ceda5c886293cf15f4e39493517a2</id>
<content type='text'>
Missing nodes may also be signaled via -ENODATA. We need to check for
that to prevent failing in non-usb3 setups.

Furthermore, dev.phy must be NULL'ed in case usb3-phy was not found.

Fixes: 142d50fbce7c ("usb: dwc3: Add support for usb3-phy PHY configuration")
Signed-off-by: Jan Kiszka &lt;jan.kiszka@siemens.com&gt;
</content>
</entry>
<entry>
<title>Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb</title>
<updated>2022-04-22T15:06:31Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-04-22T15:06:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6d73175b1f407fefc6c5a0b81ac30c6b18bcc191'/>
<id>urn:sha1:6d73175b1f407fefc6c5a0b81ac30c6b18bcc191</id>
<content type='text'>
</content>
</entry>
<entry>
<title>usb: dwc3: Add support for usb3-phy PHY configuration</title>
<updated>2022-04-22T08:35:14Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2022-03-09T09:05:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=142d50fbce7c364a74f5e8204dba491b9f066e6c'/>
<id>urn:sha1:142d50fbce7c364a74f5e8204dba491b9f066e6c</id>
<content type='text'>
When usb3-phy label is found, PHY driver is called and serdes line is
initialized. This is preparation for serdes/psgtr driver to configure GT
lines based on description in DT.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
</feed>
