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<title>u-boot.git/drivers/usb/host, branch v2015.10-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/usb/host?h=v2015.10-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/usb/host?h=v2015.10-rc2'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2015-08-17T16:49:15Z</updated>
<entry>
<title>arm: mvebu: add multiple usb-hostcontroller support for AXP</title>
<updated>2015-08-17T16:49:15Z</updated>
<author>
<name>Anton Schubert</name>
<email>anton.schubert@gmx.de</email>
</author>
<published>2015-07-23T13:02:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8a3337161d0fdedcfbe6d6be884f811496feedc1'/>
<id>urn:sha1:8a3337161d0fdedcfbe6d6be884f811496feedc1</id>
<content type='text'>
This patch adds support for multiple hostcontrollers to the ehci-marvell driver
and enables all 3 usb-hcs on the db-mv784mp-gp board.

It depends on the initial Armada XP usb support patch from Stefan.

Signed-off-by: Anton Schubert &lt;anton.schubert@gmx.de&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
</content>
</entry>
<entry>
<title>arm: mvebu: Enable USB EHCI support on Armada XP</title>
<updated>2015-08-17T16:49:07Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2015-07-22T16:26:13Z</published>
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<id>urn:sha1:dee40d26d395e6f589d3c11af20c31a154d98d41</id>
<content type='text'>
This patch enables the USB EHCI support for the Marvell Armada XP (AXP)
SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure
the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done
this already in the bin_hdr (SPL U-Boot). Without this, accessing the
controller registers in U-Boot or Linux will hang the CPU.

Additionally, the AXP uses a different USB EHCI base address. This
patch also takes care of this by runtime SoC detection in the Marvell
EHCI driver.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Anton Schubert &lt;anton.schubert@gmx.de&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
</content>
</entry>
<entry>
<title>usb: ohci: enable cache support</title>
<updated>2015-08-13T00:47:48Z</updated>
<author>
<name>Wu, Josh</name>
<email>Josh.wu@atmel.com</email>
</author>
<published>2015-07-27T03:40:18Z</published>
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<id>urn:sha1:e0266f4942f22d3111a5365f3b2c33ecd55730eb</id>
<content type='text'>
Remove the CONFIG_DM_USB limitation to enable cache support functions.
Tested on SAMA5D3x-EK board.

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
Acked-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
</content>
</entry>
<entry>
<title>dwc2: Add dcache support</title>
<updated>2015-08-13T00:47:43Z</updated>
<author>
<name>Alexander Stein</name>
<email>alexanders83@web.de</email>
</author>
<published>2015-07-24T07:22:14Z</published>
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<id>urn:sha1:db402e005a7db7c60811deb199e0df3eec479601</id>
<content type='text'>
This adds dcache support for dwc2. The DMA buffers must be DMA aligned and
is flushed for outgoing transactions before starting transfer. For
ingoing transactions it is invalidated after the transfer has finished.

Signed-off-by: Alexander Stein &lt;alexanders83@web.de&gt;
Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
[trini: Update to apply again on top of DM patches]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>sunxi: usb-phy: Never power off the usb ports</title>
<updated>2015-08-08T14:26:19Z</updated>
<author>
<name>Hans de Goede</name>
<email>hdegoede@redhat.com</email>
</author>
<published>2015-07-08T14:44:22Z</published>
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<id>urn:sha1:c9f8947e66042b49bba358d4bce531da3bd440be</id>
<content type='text'>
USB devices are not really designed to get the power bounced off and on
at them. Esp. USB powered harddisks do not like this.

Currently we power off the USB ports both on a "usb reset" and when
booting the kernel, causing the usb-power to bounce off and then back
on again.

This patch removes the powering off calls, fixing the undesirable power
bouncing.

Note this requires some special handling for the OTG port:
1) We must skip the external vbus check if we've already enabled our own
vbus to avoid false positives
2) If on an usb reset we no longer detect that the id-pin is grounded, turn
off vbus as that means an external vbus may be present now

Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Acked-by: Ian Campbell &lt;ijc@hellion.org.uk&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-dm</title>
<updated>2015-08-06T23:56:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2015-08-06T23:56:03Z</published>
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<id>urn:sha1:ae27120c31d58b8bb694d9155bcffdcfae8552a6</id>
<content type='text'>
</content>
</entry>
<entry>
<title>dm: usb: Add driver-model support to dwc2</title>
<updated>2015-08-06T13:31:37Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-07-08T02:53:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f58a41e001c5ad5b9ae7e49b37b031f7880b5638'/>
<id>urn:sha1:f58a41e001c5ad5b9ae7e49b37b031f7880b5638</id>
<content type='text'>
Add driver model support to this driver so it can be used with the new USB
stack.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: usb: Prepare dwc2 driver for driver-model conversion</title>
<updated>2015-08-06T13:31:37Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-07-08T02:53:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cc3e3a9e0eab3bc15be1766222fc2739f375252a'/>
<id>urn:sha1:cc3e3a9e0eab3bc15be1766222fc2739f375252a</id>
<content type='text'>
Put all global data in a structure and move (what will be) common code into
common functions. This will make the driver-model conversion much easier.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Tegra: clocks: Add 38.4MHz OSC support for T210 use</title>
<updated>2015-08-05T22:22:51Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2015-06-22T20:03:44Z</published>
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<id>urn:sha1:3e8650c0f9cc7fb29bd75c11d0173768fcc80203</id>
<content type='text'>
Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs
to be measured - should be close to 700MHz (1.4G/2).

Note that some freqs aren't in the PLLU table in T210 TRM
(13, 26MHz), so I used the 12MHz table entry for them. They
shouldn't be selected since they're not viable T210 OSC freqs.

Since there are now 2 new OSC defines, all tables (pll_x_table,
PLLU) had to increase by two entries, but since 38.4/48MHz are
not viable osc freqs on T20/30/114, etc, they're just set to 0.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>usb: USB storage-specific part ifdef in uclass</title>
<updated>2015-08-05T15:20:34Z</updated>
<author>
<name>Paul Kocialkowski</name>
<email>contact@paulk.fr</email>
</author>
<published>2015-08-04T15:04:12Z</published>
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<id>urn:sha1:0fa5999bea643a81072f1e71a2fae976d00018a8</id>
<content type='text'>
usb_stor_reset is only defined when USB storage support is enabled, thus the
function is not declared when such support is missing.

Signed-off-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
</content>
</entry>
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