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<title>u-boot.git/drivers/usb/host, branch v2018.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>usb: dwc2: Add reset ctrl to driver</title>
<updated>2018-08-29T01:10:30+00:00</updated>
<author>
<name>Ley Foon Tan</name>
<email>ley.foon.tan@intel.com</email>
</author>
<published>2018-08-28T16:08:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=88c34b8da62cfb4188ff9a59acb32f88ce9ed1b0'/>
<id>88c34b8da62cfb4188ff9a59acb32f88ce9ed1b0</id>
<content type='text'>
Add code to reset all reset signals as in usb DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.

If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.

Signed-off-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
</content>
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<pre>
Add code to reset all reset signals as in usb DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.

If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.

Signed-off-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: ehci: Add PHY support to ehci-pci</title>
<updated>2018-08-28T09:00:19+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-08-07T10:27:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1335e7745f77f122cf4196b8da2aa2fc5edad475'/>
<id>1335e7745f77f122cf4196b8da2aa2fc5edad475</id>
<content type='text'>
Add support for operating a PHY attached to ehci-pci. There are
systems where the EHCI controller is internally wired to a PCI
bus and has a PHY connected to it as well, ie. the R-Car Gen2.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
</content>
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<pre>
Add support for operating a PHY attached to ehci-pci. There are
systems where the EHCI controller is internally wired to a PCI
bus and has a PHY connected to it as well, ie. the R-Car Gen2.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: ehci: Make the PHY handling generic</title>
<updated>2018-08-28T09:00:18+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-08-08T12:29:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b43cdf9b3fe246a8920d2b62ee41fc1722315ef0'/>
<id>b43cdf9b3fe246a8920d2b62ee41fc1722315ef0</id>
<content type='text'>
Pull out the EHCI PHY functions into the ehci-hcd.c to let other
EHCI drivers use them.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
</content>
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<pre>
Pull out the EHCI PHY functions into the ehci-hcd.c to let other
EHCI drivers use them.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sunxi: A64: OHCI: prevent turning off shared USB clock</title>
<updated>2018-07-05T09:25:50+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2018-07-04T23:57:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0bc846a769d43810af9e4622473b85ffaead3dea'/>
<id>0bc846a769d43810af9e4622473b85ffaead3dea</id>
<content type='text'>
On the A64 the clock for the first USB controller is actually the parent
of the clock for the second controller, so turning them off in that order
makes the system hang.
Fix this by only turning off *both* clocks when the *last* OHCI controller
is brought down. This covers the case when only one controller is used.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
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<pre>
On the A64 the clock for the first USB controller is actually the parent
of the clock for the second controller, so turning them off in that order
makes the system hang.
Fix this by only turning off *both* clocks when the *last* OHCI controller
is brought down. This covers the case when only one controller is used.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: dwc2: Add brcm,bcm2708-usb compatible</title>
<updated>2018-07-05T09:25:49+00:00</updated>
<author>
<name>Emmanuel Vadot</name>
<email>manu@freebsd.org</email>
</author>
<published>2018-07-02T12:34:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ff5d5cc2331033c8a6987bb644827b52484160d9'/>
<id>ff5d5cc2331033c8a6987bb644827b52484160d9</id>
<content type='text'>
When using CONFIG_OF_BOARD on rpi to use the dtb provided by the
RaspberryPi Fundation, the compatible string isn't the same, resulting
in not-functional usb from u-boot.

Signed-off-by: Oleksandr Tymoshenko &lt;gonzo@FreeBSD.org&gt;
Signed-off-by: Emmanuel Vadot &lt;manu@freebsd.org&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When using CONFIG_OF_BOARD on rpi to use the dtb provided by the
RaspberryPi Fundation, the compatible string isn't the same, resulting
in not-functional usb from u-boot.

Signed-off-by: Oleksandr Tymoshenko &lt;gonzo@FreeBSD.org&gt;
Signed-off-by: Emmanuel Vadot &lt;manu@freebsd.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: sunxi: Use proper reg_mask for clock gate, reset</title>
<updated>2018-06-29T08:52:18+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagannadh.teki@gmail.com</email>
</author>
<published>2018-06-28T14:10:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9c22aec4102de0f0dc35e21772d9f21d4616c3d2'/>
<id>9c22aec4102de0f0dc35e21772d9f21d4616c3d2</id>
<content type='text'>
Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.

unfortunately these are fixed due to lack of separate
clock, reset drivers.

Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.

This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.

We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.

unfortunately these are fixed due to lack of separate
clock, reset drivers.

Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.

This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.

We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: ohci: change the NUM_EDs from 8 to 32</title>
<updated>2018-06-29T08:52:12+00:00</updated>
<author>
<name>Zeng Tao</name>
<email>prime.zeng@hisilicon.com</email>
</author>
<published>2018-06-28T17:54:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=11080bf6c705ca1ebed23417204a73738bd81669'/>
<id>11080bf6c705ca1ebed23417204a73738bd81669</id>
<content type='text'>
For ohci, the maximam supported endpoint number is 32(in and out), and
now we have used (usb_pipeendpoint(pipe) &lt;&lt; 1) to index the specified
endpoint descritor, usb_pipeendpoint(pipe) can reach 0xf, so we need
change the NUM_EDs from 8 to 32.

Signed-off-by: Zeng Tao &lt;prime.zeng@hisilicon.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For ohci, the maximam supported endpoint number is 32(in and out), and
now we have used (usb_pipeendpoint(pipe) &lt;&lt; 1) to index the specified
endpoint descritor, usb_pipeendpoint(pipe) can reach 0xf, so we need
change the NUM_EDs from 8 to 32.

Signed-off-by: Zeng Tao &lt;prime.zeng@hisilicon.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: sunxi: ohci: make ohci_t the first member in private data</title>
<updated>2018-06-29T08:52:07+00:00</updated>
<author>
<name>Vasily Khoruzhick</name>
<email>anarsoul@gmail.com</email>
</author>
<published>2018-06-17T16:13:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ebbc23a0495cd189cda2760f66cc0195dd030a19'/>
<id>ebbc23a0495cd189cda2760f66cc0195dd030a19</id>
<content type='text'>
ohci-hcd casts priv_data pointer to (ohci_t *), thus it must be
the first member in private data struct.

Fixes 831cc98b1 ("usb: sunxi: Simplify ccm reg base code")

Signed-off-by: Vasily Khoruzhick &lt;anarsoul@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
ohci-hcd casts priv_data pointer to (ohci_t *), thus it must be
the first member in private data struct.

Fixes 831cc98b1 ("usb: sunxi: Simplify ccm reg base code")

Signed-off-by: Vasily Khoruzhick &lt;anarsoul@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-usb</title>
<updated>2018-06-16T04:07:37+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-06-16T04:07:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a715415bb5948c84cc44c601b193188990f7238b'/>
<id>a715415bb5948c84cc44c601b193188990f7238b</id>
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</content>
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<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: sunxi: access ahb_reset0_cfg in CCM using its offset</title>
<updated>2018-06-14T10:57:19+00:00</updated>
<author>
<name>Vasily Khoruzhick</name>
<email>anarsoul@gmail.com</email>
</author>
<published>2018-06-14T06:19:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b9f34757db5dcde9ccfa6ce35705b025bc4843fc'/>
<id>b9f34757db5dcde9ccfa6ce35705b025bc4843fc</id>
<content type='text'>
struct sunxi_ccm_reg doesn't have ahb_reset0_cfg on sun4i and sun5i,
thus compilation fails with:

drivers/usb/host/ohci-sunxi.c:96:26: error: 'struct sunxi_ccm_reg' has
no member named 'ahb_reset0_cfg'

Access this reg using its offset to fix this issue.

Fixes commit 1ed9c1118 ("usb: sunxi: ehci: get rid of ifdefs")
and commit 56830cee3 ("usb: sunxi: ohci: get rid of ifdefs")

Signed-off-by: Vasily Khoruzhick &lt;anarsoul@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
struct sunxi_ccm_reg doesn't have ahb_reset0_cfg on sun4i and sun5i,
thus compilation fails with:

drivers/usb/host/ohci-sunxi.c:96:26: error: 'struct sunxi_ccm_reg' has
no member named 'ahb_reset0_cfg'

Access this reg using its offset to fix this issue.

Fixes commit 1ed9c1118 ("usb: sunxi: ehci: get rid of ifdefs")
and commit 56830cee3 ("usb: sunxi: ohci: get rid of ifdefs")

Signed-off-by: Vasily Khoruzhick &lt;anarsoul@gmail.com&gt;
</pre>
</div>
</content>
</entry>
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