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<title>u-boot.git/drivers/video/ipu_common.c, branch v2013.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/video/ipu_common.c?h=v2013.01-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/video/ipu_common.c?h=v2013.01-rc2'/>
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<updated>2012-11-06T21:24:11Z</updated>
<entry>
<title>ipu common: reset ipuv3 correctly</title>
<updated>2012-11-06T21:24:11Z</updated>
<author>
<name>Liu Ying</name>
<email>Ying.Liu@freescale.com</email>
</author>
<published>2012-10-06T04:16:04Z</published>
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<id>urn:sha1:945d069fb5c8932e74aeba178c60a9dc6e9cba93</id>
<content type='text'>
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
cleared by the hardware automatically within
10 millisecond.

Signed-off-by: Liu Ying &lt;Ying.Liu@freescale.com&gt;
</content>
</entry>
<entry>
<title>mx5: Use explicit clock gate names</title>
<updated>2012-10-15T18:54:10Z</updated>
<author>
<name>Benoît Thébaudeau</name>
<email>benoit.thebaudeau@advansee.com</email>
</author>
<published>2012-09-27T10:21:00Z</published>
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<id>urn:sha1:1f5e4ee0b9e06a129a6a1b117d77c77189c18542</id>
<content type='text'>
Use clock gate definitions having names showing clearly the gated clock instead
of names giving only a register field index.

Signed-off-by: Benoît Thébaudeau &lt;benoit.thebaudeau@advansee.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fields</title>
<updated>2012-10-15T18:54:08Z</updated>
<author>
<name>Eric Nelson</name>
<email>eric.nelson@boundarydevices.com</email>
</author>
<published>2012-09-21T07:33:51Z</published>
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<id>urn:sha1:0bb7e316f0ba1899ef2e94d75510c043683c212f</id>
<content type='text'>
Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.

Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:

     http://patchwork.ozlabs.org/patch/185129/

Signed-off-by: Eric Nelson &lt;eric.nelson@boundarydevices.com&gt;
</content>
</entry>
<entry>
<title>ipu_common: Add ldb_clk for use in parenting the pixel clock</title>
<updated>2012-07-10T09:35:39Z</updated>
<author>
<name>Eric Nelson</name>
<email>eric.nelson@boundarydevices.com</email>
</author>
<published>2012-05-31T07:24:02Z</published>
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<id>urn:sha1:cf65d478ab4e0bb0247c374e6b0b40ef77eddbe8</id>
<content type='text'>
Add ldb_clk for use in parenting the pixel clock.

Signed-off-by: Eric Nelson &lt;eric.nelson@boundarydevices.com&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>ipu_common: Do not hardcode the ipu_clk frequency</title>
<updated>2012-07-10T09:35:39Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2012-05-31T07:24:00Z</published>
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<id>urn:sha1:9fbdb1aac5583197270c5d1a7634b7f93b34a654</id>
<content type='text'>
Do not hardcode the ipu_clk frequency and let the board file pass this value.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>ipu_common: Rename MXC_CCM_BASE</title>
<updated>2012-07-10T09:35:39Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2012-05-31T07:23:59Z</published>
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<id>urn:sha1:477bca22f6bb649fb4c55d3ee401ff0f3c0c0e9e</id>
<content type='text'>
Rename MXC_CCM_BASE to CCM_BASE_ADDR as this is already defined for MX6.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53</title>
<updated>2012-07-10T09:35:39Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2012-05-31T07:23:58Z</published>
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<id>urn:sha1:e4942ad703d81bc800210de3f4ba27a2f8178eb3</id>
<content type='text'>
The registers accessed inside clk_ipu_enable/disable are not present on MX6,
so make sure they only run on MX51 and MX53.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>ipu_common: Only apply the erratum to MX51</title>
<updated>2012-07-10T09:35:38Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2012-05-31T07:23:57Z</published>
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<id>urn:sha1:913db79427ba6fc71a179a6faff96756ebf40980</id>
<content type='text'>
The following erratum :

"ENGcm08316
IPU: Clarification regarding the bypass mode registers setup for
display and camera interfaces"

only applies to mx51, so restrict its usage for this SoC only.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>MX51: Add IPU driver for video support</title>
<updated>2010-10-21T22:05:05Z</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2010-10-13T10:16:35Z</published>
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<id>urn:sha1:575001e40c9d10e63f2924649098e7c07d3985c7</id>
<content type='text'>
The patch is a porting of the IPU Linux driver
developed by Freescale to have framebuffer
functionalities in u-boot. The port is based on
kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f,
as delivered by Freescale [i.MX BSP].
Most features are dropped from the original driver and
only LCD support is the goal of this porting.

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
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