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<title>u-boot.git/drivers/video/ipu_common.c, branch v2016.01-rc3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/video/ipu_common.c?h=v2016.01-rc3</id>
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<updated>2015-04-20T07:36:59Z</updated>
<entry>
<title>video, ipu: make ldb clock frequency overwritable through board code</title>
<updated>2015-04-20T07:36:59Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2015-04-20T05:53:48Z</published>
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<id>urn:sha1:cb9f8e6a737e60f460896111b32bbebc45aa1cd1</id>
<content type='text'>
the ldb clock can be setup in board code (for example set through PLL5).
Update the ldb_clock rate also through board code.

This should be removed, if a clock framework is availiable.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
Tested-by: Eric Nelson &lt;eric.nelson@boundarydevices.com&gt;
</content>
</entry>
<entry>
<title>video, ipu: make ldb_clock configurable</title>
<updated>2015-04-20T07:34:45Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2015-04-20T05:52:21Z</published>
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<id>urn:sha1:0ced25beb5c0ee6aefe183c980560bed3d664fdb</id>
<content type='text'>
make the ldb_clock configurable through the new define
CONFIG_SYS_LDB_CLOCK. This is needed as the ldb clock is not
always 650000000, for example on the aristainetos2 board,
where the ldb clock derives from PLL5 clock.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
Tested-by: Eric Nelson &lt;eric.nelson@boundarydevices.com&gt;
</content>
</entry>
<entry>
<title>video: ipu: prevent warnings with W=1</title>
<updated>2014-10-25T11:27:37Z</updated>
<author>
<name>Jeroen Hofstee</name>
<email>jeroen@myspectrum.nl</email>
</author>
<published>2014-10-08T20:57:47Z</published>
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<id>urn:sha1:c5fe2532acf61acdc8da459110dbf4ad56496cb1</id>
<content type='text'>
- make local functions static
- remove unused is_interlaced function

Signed-off-by: Jeroen Hofstee &lt;jeroen@myspectrum.nl&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19Z</published>
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<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>ipu common: reset ipuv3 correctly</title>
<updated>2012-11-06T21:24:11Z</updated>
<author>
<name>Liu Ying</name>
<email>Ying.Liu@freescale.com</email>
</author>
<published>2012-10-06T04:16:04Z</published>
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<id>urn:sha1:945d069fb5c8932e74aeba178c60a9dc6e9cba93</id>
<content type='text'>
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
cleared by the hardware automatically within
10 millisecond.

Signed-off-by: Liu Ying &lt;Ying.Liu@freescale.com&gt;
</content>
</entry>
<entry>
<title>mx5: Use explicit clock gate names</title>
<updated>2012-10-15T18:54:10Z</updated>
<author>
<name>Benoît Thébaudeau</name>
<email>benoit.thebaudeau@advansee.com</email>
</author>
<published>2012-09-27T10:21:00Z</published>
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<id>urn:sha1:1f5e4ee0b9e06a129a6a1b117d77c77189c18542</id>
<content type='text'>
Use clock gate definitions having names showing clearly the gated clock instead
of names giving only a register field index.

Signed-off-by: Benoît Thébaudeau &lt;benoit.thebaudeau@advansee.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fields</title>
<updated>2012-10-15T18:54:08Z</updated>
<author>
<name>Eric Nelson</name>
<email>eric.nelson@boundarydevices.com</email>
</author>
<published>2012-09-21T07:33:51Z</published>
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<id>urn:sha1:0bb7e316f0ba1899ef2e94d75510c043683c212f</id>
<content type='text'>
Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.

Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:

     http://patchwork.ozlabs.org/patch/185129/

Signed-off-by: Eric Nelson &lt;eric.nelson@boundarydevices.com&gt;
</content>
</entry>
<entry>
<title>ipu_common: Add ldb_clk for use in parenting the pixel clock</title>
<updated>2012-07-10T09:35:39Z</updated>
<author>
<name>Eric Nelson</name>
<email>eric.nelson@boundarydevices.com</email>
</author>
<published>2012-05-31T07:24:02Z</published>
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<id>urn:sha1:cf65d478ab4e0bb0247c374e6b0b40ef77eddbe8</id>
<content type='text'>
Add ldb_clk for use in parenting the pixel clock.

Signed-off-by: Eric Nelson &lt;eric.nelson@boundarydevices.com&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>ipu_common: Do not hardcode the ipu_clk frequency</title>
<updated>2012-07-10T09:35:39Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2012-05-31T07:24:00Z</published>
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<id>urn:sha1:9fbdb1aac5583197270c5d1a7634b7f93b34a654</id>
<content type='text'>
Do not hardcode the ipu_clk frequency and let the board file pass this value.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>ipu_common: Rename MXC_CCM_BASE</title>
<updated>2012-07-10T09:35:39Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2012-05-31T07:23:59Z</published>
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<id>urn:sha1:477bca22f6bb649fb4c55d3ee401ff0f3c0c0e9e</id>
<content type='text'>
Rename MXC_CCM_BASE to CCM_BASE_ADDR as this is already defined for MX6.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
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