u-boot.git/drivers/video/ipu_common.c, branch v2017.03-rc2

treewide: replace #include with

2016-09-23T21:55:42Z

Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap ) Replace all include directives for with . Signed-off-by: Masahiro Yamada [trini: Fixup include/clk.] Signed-off-by: Tom Rini

video: ipu_common: fix build error

2016-04-28T14:28:45Z

Some toolchains fail to build "clk->rate = (u64)(clk->parent->rate * 16) / div;" And the cast usage is wrong. Use the following code to fix the issue, " do_div(parent_rate, div); clk->rate = parent_rate; " Reported-by: Peter Robinson Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Cc: Tom Rini Cc: Anatolij Gustschin Cc: Peter Robinson Reviewed-by: Tom Rini Tested-by: Peter Robinson

video: ipu: avoid overflow issue

2016-03-14T21:47:41Z

Multiplication, as "clk->parent->rate * 16" may overflow. So use do_div to avoid such issue. Signed-off-by: Peng Fan Signed-off-by: Sandor Yu Cc: Anatolij Gustschin Cc: Stefano Babic Cc: Fabio Estevam

video, ipu: make ldb clock frequency overwritable through board code

2015-04-20T07:36:59Z

the ldb clock can be setup in board code (for example set through PLL5). Update the ldb_clock rate also through board code. This should be removed, if a clock framework is availiable. Signed-off-by: Heiko Schocher Tested-by: Eric Nelson

video, ipu: make ldb_clock configurable

2015-04-20T07:34:45Z

make the ldb_clock configurable through the new define CONFIG_SYS_LDB_CLOCK. This is needed as the ldb clock is not always 650000000, for example on the aristainetos2 board, where the ldb clock derives from PLL5 clock. Signed-off-by: Heiko Schocher Tested-by: Eric Nelson

video: ipu: prevent warnings with W=1

2014-10-25T11:27:37Z

- make local functions static - remove unused is_interlaced function Signed-off-by: Jeroen Hofstee

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38Z

Signed-off-by: Wolfgang Denk [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini

ipu common: reset ipuv3 correctly

2012-11-06T21:24:11Z

This patch checks self-clear sw_ipu_rst bit in SCR register of SRC controller to be cleared after setting it to high to reset IPUv3. This makes sure that IPUv3 finishes sofware reset. A timeout mechanism is added to stop polling on the bit status in case the bit could not be cleared by the hardware automatically within 10 millisecond. Signed-off-by: Liu Ying

mx5: Use explicit clock gate names

2012-10-15T18:54:10Z

Use clock gate definitions having names showing clearly the gated clock instead of names giving only a register field index. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic

i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fields

2012-10-15T18:54:08Z

Add meaningful constants for each clock channels and use them for enabling and disabling i.MX6 clocks. Includes an update to enable/disable the IPU1 clock in drivers/video/ipu_common to remove IMX5x register access when used on i.MX6 as discussed in V1: http://patchwork.ozlabs.org/patch/185129/ Signed-off-by: Eric Nelson