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<title>u-boot.git/drivers/video/rockchip, branch v2016.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/video/rockchip?h=v2016.07</id>
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<updated>2016-07-05T16:38:56Z</updated>
<entry>
<title>rockchip: video: Lower hpd wait time</title>
<updated>2016-07-05T16:38:56Z</updated>
<author>
<name>Sjoerd Simons</name>
<email>sjoerd.simons@collabora.co.uk</email>
</author>
<published>2016-02-28T21:40:02Z</published>
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<id>urn:sha1:70c440e5bdca097915b71170f9532ae4faad735a</id>
<content type='text'>
Waiting 30 seconds for the hpd to go high seems a bit much, especially
on headless boots. Lowering the timeout to 300ms.

Sending as RFC because frankly i don't know what a sensible timeout is
here, but 30 seconds is clearly not it :)

Signed-off-by: Sjoerd Simons &lt;sjoerd.simons@collabora.co.uk&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Dropped RFC tag:
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: convert API to match reset/mailbox style</title>
<updated>2016-06-19T23:05:55Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-06-17T15:44:00Z</published>
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<id>urn:sha1:135aa95002646c46e89de93fa36adad1b010548f</id>
<content type='text'>
The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
  provider now implements a single set of clocks. This provides a simpler
  conceptual interface to clients, and better aligns with device tree
  clock bindings.
* Clocks are now identified with a single "struct clk", rather than
  requiring clients to store the clock provider device and clock identity
  values separately. For simple clock consumers, this isolates clients
  from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
  clk-uclass.h contains the provider API. This aligns with the recently
  added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
  can customize these operations if needed. This also aligns with the
  recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
  clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst
others).

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: video: Flush the cache when the display is updated</title>
<updated>2016-05-27T16:23:08Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-14T20:03:01Z</published>
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<id>urn:sha1:b55e04a021ee256aaba118a547f13a4722538623</id>
<content type='text'>
Enable this option to correct display artifacts when a write-back cache is
in use.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: video: Add LVDS support in vop driver</title>
<updated>2016-03-14T21:24:10Z</updated>
<author>
<name>Jacob Chen</name>
<email>jacob-chen@iotwrt.com</email>
</author>
<published>2016-03-14T03:20:18Z</published>
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<id>urn:sha1:8530783594f6de14ec6d4b7bf804437d6e1a4f5f</id>
<content type='text'>
LVDS have a different display out mode, add code to get right flag.

The vop_ip decide display device and the remote_vop_id decide which
vop was being used. So we should use the remote_vop_id to set DCLK_VOP.

Signed-off-by: Jacob Chen &lt;jacob-chen@iotwrt.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: video: Add a display driver for rockchip LVDS</title>
<updated>2016-03-14T21:06:33Z</updated>
<author>
<name>Jacob Chen</name>
<email>jacob-chen@iotwrt.com</email>
</author>
<published>2016-03-14T03:20:16Z</published>
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<id>urn:sha1:35ac89dd8fe7e9373d8c4336e7fbe93ae3fd59d7</id>
<content type='text'>
Some Rockchip SoCs support LVDS output. Add a display driver for this so
that these displays can be used on supported boards.

Signed-off-by: Jacob Chen &lt;jacob-chen@iotwrt.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: video: Add a video-output driver</title>
<updated>2016-01-22T03:42:36Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-22T02:45:05Z</published>
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<id>urn:sha1:7b7ad5c31c91f84ae12b9a7ec850b5d0f720e19b</id>
<content type='text'>
Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: video: Add a display driver for rockchip eDP</title>
<updated>2016-01-22T03:42:36Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-22T02:45:04Z</published>
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<id>urn:sha1:5852d539eab0e0a7f7a600cb57459091773c6c4a</id>
<content type='text'>
Some Rockchip SoCs support embedded DisplayPort output. Add a display driver
for this so that these displays can be used on supported boards.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: video: Add a display driver for rockchip HDMI</title>
<updated>2016-01-22T03:42:36Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-22T02:45:03Z</published>
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<id>urn:sha1:c2539483416a3237ae6d7f2d15fe468c4e771223</id>
<content type='text'>
Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.

Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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