u-boot.git/drivers/video/zynqmp, branch master Unnamed repository; edit this file 'description' to name the repository. treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage 2026-02-17T19:50:22+00:00 Peng Fan peng.fan@nxp.com 2026-02-09T01:30:18+00:00 0f90b1e715f8abe41b0875752eb184f46032ff11 Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and drop the unnecessary inclusion of asm/global_data.h. Headers should be included directly by the files that need them, rather than indirectly via global_data.h. Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> #STMicroelectronics boards and STM32MP1 ram test driver Tested-by: Anshul Dalal <anshuld@ti.com> #TI boards Acked-by: Yao Zi <me@ziyao.cc> #TH1520 Signed-off-by: Peng Fan <peng.fan@nxp.com> 
Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.

Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal <anshuld@ti.com> #TI boards
Acked-by: Yao Zi <me@ziyao.cc> #TH1520
Signed-off-by: Peng Fan <peng.fan@nxp.com>
video: zynqmp: Prevent use of uninitialised variables 2025-10-09T10:31:09+00:00 Andrew Goodbody andrew.goodbody@linaro.org 2025-10-01T16:36:43+00:00 4c606b165b51b5e0ac8a3ecc8edd232345340145 The variables 'offset_matrix' and 'csc_matrix' will be used uninitialised if video->is_rgb is false. Correct the logic so the attempt to use uninitialised variables is not made. Also remove the use of these variables as they seem to serve no useful purpose just being aliases for arrays. This issue was found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Link: https://lore.kernel.org/r/20251001-video_zynqmp-v1-1-34f1e59b9c34@linaro.org Signed-off-by: Michal Simek <michal.simek@amd.com> 
The variables 'offset_matrix' and 'csc_matrix' will be used
uninitialised if video->is_rgb is false. Correct the logic so the
attempt to use uninitialised variables is not made. Also remove the use
of these variables as they seem to serve no useful purpose just being
aliases for arrays.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20251001-video_zynqmp-v1-1-34f1e59b9c34@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
drivers: use lowercase hex prefix style 2025-06-14T15:09:39+00:00 E Shattow e@freeshell.de 2025-06-06T22:44:58+00:00 449a5566522f07b4c8d58f3a6bdc36a74400e672 Use consistent lowercase hex prefix style in drivers/* Does not change hex prefix case in allcaps uppercase style error messages Signed-off-by: E Shattow <e@freeshell.de> 
Use consistent lowercase hex prefix style in drivers/*

Does not change hex prefix case in allcaps uppercase style error messages

Signed-off-by: E Shattow <e@freeshell.de>
video: zynqmp: Add support for reset 2024-12-11T11:40:13+00:00 Michal Simek michal.simek@amd.com 2024-12-09T11:11:50+00:00 8b81010a2fe385524b58bea9116f1b6954c3d2bd In Kria SOM configuration DP is under reset and access to DP is causing hang that's why call reset at probe to avoid this situation. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0504474a91a9839828aecd37f8855fd154cdf2e1.1733742708.git.michal.simek@amd.com 
In Kria SOM configuration DP is under reset and access to DP is causing
hang that's why call reset at probe to avoid this situation.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0504474a91a9839828aecd37f8855fd154cdf2e1.1733742708.git.michal.simek@amd.com
zynqmp: Avoid setting the framebuffer address 2024-08-26T20:05:38+00:00 Simon Glass sjg@chromium.org 2024-08-21T16:19:00+00:00 3876abbbfc2715d148b46de10c0827eb2cd387f7 This is handled by driver model so this driver should not be setting the framebuffer address. Drop the assignment. Signed-off-by: Simon Glass <sjg@chromium.org> 
This is handled by driver model so this driver should not be setting the
framebuffer address. Drop the assignment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet" 2024-05-20T19:35:03+00:00 Tom Rini trini@konsulko.com 2024-05-20T19:35:03+00:00 03de305ec48b0bb28554372abb40ccd46dbe0bf9 As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> 
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" 2024-05-19T14:16:36+00:00 Tom Rini trini@konsulko.com 2024-05-19T02:20:43+00:00 d678a59d2d719da9e807495b4b021501f2836ca5 When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> 
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
video: Remove <common.h> and add needed includes 2024-05-07T14:00:57+00:00 Tom Rini trini@konsulko.com 2024-05-02T01:31:31+00:00 a2955579e737acf24ad76da4f9d42066ac9d135b Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> 
Remove <common.h> from this driver directory and when needed
add missing include files directly.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
video: zynqmp: Enable 1024x768 resolution 2023-06-12T11:25:02+00:00 Michal Simek michal.simek@amd.com 2023-05-17T08:42:12+00:00 322c0da86aa8ba72dd5cbcd83db60d4d3d8af4de Add support for 1024x768 60p resolution and set it up this resolution by default. This resolution is still able to use only one GT line. But for example 800x600 60p has some issues with settings. That's why extend this table by tested resolutions. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/957e1e85a05744326ec2606dadc1af6e69976f37.1684312924.git.michal.simek@amd.com 
Add support for 1024x768 60p resolution and set it up this resolution by
default. This resolution is still able to use only one GT line. But for
example 800x600 60p has some issues with settings. That's why extend this
table by tested resolutions.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/957e1e85a05744326ec2606dadc1af6e69976f37.1684312924.git.michal.simek@amd.com
video: zynqmp: Driver for Xilinx ZynqMP DisplayPort Subsystem 2023-06-12T11:25:01+00:00 Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com 2023-05-17T08:42:10+00:00 a29f44d631acfb123a5c810561066b14c8a037b2 The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort Subsystem. It includes a buffer manager, blender, an audio mixer and a DisplayPort source controller (transmitter). The DisplayPort controller can source data from memory (non-live input) or the stream (live input). The DisplayPort controller is responsible for managing the link and physical layer functionality. The controller packs audio/video data into transfer units and sends them over the main link. The link rate and lane counts can be selected based on the application bandwidth requirements. The DisplayPort pipeline consists of the DisplayPort direct memory access (DMA) for fetching data from memory. The DisplayPort DMA controller (DPDMA) supports up to six input channels as non-live input. This driver supports the DisplayPort Subsystem and implements 1)640x480 resolution 2)RGBA8888 32bpp format 3)DPDMA channel 3 for Graphics 4)Non-live input 5)Fixed 5.4G link rate 6)Tested on ZCU102 board There will be additional work to configure GT lines based on DT, higher resolutions, support for more compressed video formats, spliting code to more files, add support for EDID, audio support, using clock framework for all clocks and in general code clean up. Codevelop-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5c1567b63d0280dacc7efba2998857c399c25358.1684312924.git.michal.simek@amd.com 
The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort
Subsystem. It includes a buffer manager, blender, an audio mixer and a
DisplayPort source controller (transmitter). The DisplayPort controller can
source data from memory (non-live input) or the stream (live input). The
DisplayPort controller is responsible for managing the link and physical
layer functionality. The controller packs audio/video data into transfer
units and sends them over the main link. The link rate and lane counts can
be selected based on the application bandwidth requirements. The
DisplayPort pipeline consists of the DisplayPort direct memory access (DMA)
for fetching data from memory. The DisplayPort DMA controller (DPDMA)
supports up to six input channels as non-live input.

This driver supports the DisplayPort Subsystem and implements
1)640x480 resolution
2)RGBA8888 32bpp format
3)DPDMA channel 3 for Graphics
4)Non-live input
5)Fixed 5.4G link rate
6)Tested on ZCU102 board

There will be additional work to configure GT lines based on DT, higher
resolutions, support for more compressed video formats, spliting code to
more files, add support for EDID, audio support, using clock framework for
all clocks and in general code clean up.

Codevelop-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5c1567b63d0280dacc7efba2998857c399c25358.1684312924.git.michal.simek@amd.com