u-boot.git/drivers/watchdog/Makefile, branch v2017.07

dm: watchdog: add BCM6345 watchdog driver

2017-05-31T12:49:54Z

This driver is a simplified version of linux/drivers/watchdog/bcm63xx_wdt.c Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass

bcm2835_wdt: support for the BCM2835/2836 watchdog

2017-05-10T00:30:08Z

Signed-off-by: Paolo Pisati

aspeed: Watchdog Timer Driver

2017-05-08T15:57:31Z

This driver supports ast2500 and ast2400 SoCs. Only ast2500 supports reset_mask and thus the option of resettting individual peripherals using WDT. Signed-off-by: Maxim Sloyko Reviewed-by: Simon Glass

dm: Simple Watchdog uclass

2017-05-08T15:57:30Z

This is a simple uclass for Watchdog Timers. It has four operations: start, restart, reset, stop. Drivers must implement start, restart and stop operations, while implementing reset is optional: It's default implementation expires watchdog timer in one clock tick. Signed-off-by: Maxim Sloyko Reviewed-by: Simon Glass

drivers: remove Blackfin specific drivers

2017-04-18T14:29:14Z

These drivers have no user since commit ea3310e8aafa ("Blackfin: Remove"). Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass Acked-by: Michal Simek Acked-by: Jaehoon Chung

wdog: Add the watchdog driver for MX7ULP.

2017-03-17T08:27:08Z

This driver implements the HW WATCHDOG functions. Which needs to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for mx7ulp. Use watchdog for reset cpu. Implement this in the driver. Need to define CONFIG_ULP_WATCHDOG to build it. Signed-off-by: Peng Fan Signed-off-by: Ye Li Cc: Stefano Babic

ls102xa: Fix reset hang

2015-10-12T16:56:32Z

Since commit 623d96e89aca6("imx: wdog: correct wcr register settings") issuing a 'reset' command causes the system to hang. Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian. This means that the watchdog on LS1021 has been working by accident as it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c. Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only revelead the endianness problem on LS102x. In order to fix the reset hang, introduce a reset_cpu() implementation that is specific for ls102x, which accesses the watchdog WCR register in big-endian format. All that is required to reset LS102x is to clear the SRS bit. This approach is a temporary workaround to avoid a regression for LS102x in the 2015.10 release. The proper fix is to make the watchdog driver endian-aware, so that it can work for i.MX, Vybrid and LS102x. Reported-by: Sinan Akman Tested-by: Sinan Akman Reviewed-by: Wolfgang Denk Signed-off-by: Fabio Estevam

imx: imx7d: add imx-common cpu support for imx7d

2015-09-13T08:11:54Z

Add imx-common cpu support for imx7d SoC - Update reset_cause for imx7d - Enable watchdog driver built for imx7d Signed-off-by: Adrian Alonso Signed-off-by: Peng Fan

ARM: remove tnetv107x board support

2015-02-24T22:07:24Z

This is still a non-generic board. Signed-off-by: Masahiro Yamada Cc: Chan-Taek Park Acked-by: Marek Vasut

arm: ls102xa: Add Freescale LS102xA SoC support

2014-09-08T17:30:32Z

The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang Signed-off-by: Jason Jin Signed-off-by: Jingchang Lu Signed-off-by: Prabhakar Kushwaha