u-boot.git/drivers/watchdog, branch v2017.05

drivers: remove Blackfin specific drivers

2017-04-18T14:29:14+00:00

These drivers have no user since commit ea3310e8aafa ("Blackfin:
Remove").

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
Acked-by: Michal Simek 
Acked-by: Jaehoon Chung

ti: wdt: omap: Disable watchdog timer before performing initialization

2017-04-09T01:32:49+00:00

The OMAP WDT IP block requires to be stopped before any write to its
registers is performed.

This problem has been thoroughly described in Linux kernel:

"watchdog: omap: assert the counter being stopped before reprogramming:
SHA1: 530c11d432727c697629ad5f9d00ee8e2864d453

Signed-off-by: Lukasz Majewski 
Reviewed-by: Tom Rini

wdog: Add the watchdog driver for MX7ULP.

2017-03-17T08:27:08+00:00

This driver implements the HW WATCHDOG functions. Which needs
to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for
mx7ulp.

Use watchdog for reset cpu. Implement this in the driver.
Need to define CONFIG_ULP_WATCHDOG to build it.

Signed-off-by: Peng Fan 
Signed-off-by: Ye Li 
Cc: Stefano Babic

imx_watchdog: Do not assert WDOG_B on watchdog init

2016-10-04T10:01:14+00:00

Currently the driver asserts WDOG_B by clearing WCR_WDA bit when
enabling the watchdog. Do not clear WCR_WDA.

Signed-off-by: Ross Parker 
Cc: Stefano Babic

imx_watchdog: add weak attribute to reset_cpu function

2016-07-19T17:52:15+00:00

This allows to overwrite reset_cpu function in case a board level
reset is preferred (e.g. through PMIC).

Signed-off-by: Stefan Agner

imx_watchdog: always set minimal timeout in reset_cpu

2016-01-07T16:54:53+00:00

The problem is that timeout bits in WCR register were leaved unchanged.
So previously set timeout value was applied and therefore 'reset'
command takes any value up to two minutes, depending on previous
watchdog settings, instead of minimal 0.5 seconds.

Signed-off-by: Andrey Skvortsov

ls102xa: Fix reset hang

2015-10-12T16:56:32+00:00

Since commit 623d96e89aca6("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.

Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.

This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.

In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.

This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.

Reported-by: Sinan Akman 
Tested-by: Sinan Akman 
Reviewed-by: Wolfgang Denk 
Signed-off-by: Fabio Estevam

imx_watchdog: Add a header file for watchdog registers

2015-10-12T16:56:26+00:00

Create fsl_wdog.h to store the watchdog registers and bit fields.

This can be useful when accesses to the watchdog block are made from other
parts, such as arch/arm/ cpu code.

Signed-off-by: Fabio Estevam

imx: wdog: correct wcr register settings

2015-09-20T07:39:35+00:00

We should not simple use "writew(WCR_WDE, &wdog->wcr)" to set
wcr, since this will override bits set before reset_cpu.

Use clrsetbits_le16 instead of writew to fix this issue.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Sebastian Siewior 
Tested-by: Fabio Estevam

imx: imx7d: add imx-common cpu support for imx7d

2015-09-13T08:11:54+00:00

Add imx-common cpu support for imx7d SoC
- Update reset_cause for imx7d
- Enable watchdog driver built for imx7d

Signed-off-by: Adrian Alonso 
Signed-off-by: Peng Fan