<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/watchdog, branch v2021.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/watchdog?h=v2021.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/watchdog?h=v2021.01'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2020-12-02T21:21:58Z</updated>
<entry>
<title>watchdog: sbsa: timeout should be in "millisecond"</title>
<updated>2020-12-02T21:21:58Z</updated>
<author>
<name>Zhao Qiang</name>
<email>qiang.zhao@nxp.com</email>
</author>
<published>2020-11-25T04:55:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c2ba01c082b4ab21e43bb15e1c3a7e19573d1133'/>
<id>urn:sha1:c2ba01c082b4ab21e43bb15e1c3a7e19573d1133</id>
<content type='text'>
timeout should be in "millisecond" instead of second,
so divided it by 1000 when calculate the load value.

Signed-off-by: Zhao Qiang &lt;qiang.zhao@nxp.com&gt;
</content>
</entry>
<entry>
<title>watchdog: Hide WATCHDOG_RESET_DISABLE</title>
<updated>2020-11-01T14:57:35Z</updated>
<author>
<name>Michael Walle</name>
<email>michael@walle.cc</email>
</author>
<published>2020-09-24T08:09:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=95b3d6a4191a5708f1259255fea6cf22f7dc2135'/>
<id>urn:sha1:95b3d6a4191a5708f1259255fea6cf22f7dc2135</id>
<content type='text'>
This option is only supported by the IMX watchdog and seems to be
similar to CONFIG_WATCHDOG.

Move it below the IMX watchdog and make it dependent on IMX_WATCHDOG.

Signed-off-by: Michael Walle &lt;michael@walle.cc&gt;
</content>
</entry>
<entry>
<title>watchdog: octeontx_wdt: Add support for start and stop</title>
<updated>2020-10-16T11:55:04Z</updated>
<author>
<name>Suneel Garapati</name>
<email>sgarapati@marvell.com</email>
</author>
<published>2020-09-23T09:01:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3981cdd8db26b65cc89d7ff5bdc668c436a4c616'/>
<id>urn:sha1:3981cdd8db26b65cc89d7ff5bdc668c436a4c616</id>
<content type='text'>
This patch enhances the Octeon TX/TX2 watchdog driver to fully enable
the WDT. With this changes, the "wdt" command is now also supported
on these platforms.

Signed-off-by: Suneel Garapati &lt;sgarapati@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Aaron Williams &lt;awilliams@marvell.com&gt;
Cc: Suneel Garapati &lt;sgarapati@marvell.com&gt;
Cc: Chandrakala Chavva &lt;cchavva@marvell.com&gt;
</content>
</entry>
<entry>
<title>wdt: designware: fix timeout calculation due to expecting KHz</title>
<updated>2020-10-08T15:42:36Z</updated>
<author>
<name>Jack Mitchell</name>
<email>ml@embed.me.uk</email>
</author>
<published>2020-09-17T09:30:40Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d9b9c91b5d0ee1044cc638f7ea809a3836cf168e'/>
<id>urn:sha1:d9b9c91b5d0ee1044cc638f7ea809a3836cf168e</id>
<content type='text'>
The timeout calculation is based on the clk being in KHz but
the clk api returns the clk value in Hz. Convert this to KHz
to calculate the correct timeout value.

Signed-off-by: Jack Mitchell &lt;ml@embed.me.uk&gt;
</content>
</entry>
<entry>
<title>watchdog: Add reset support for OcteonTX / TX2</title>
<updated>2020-08-25T06:01:16Z</updated>
<author>
<name>Suneel Garapati</name>
<email>sgarapati@marvell.com</email>
</author>
<published>2019-10-21T23:09:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=af6ba90048afb4e0db3ff2480364286f230f8b91'/>
<id>urn:sha1:af6ba90048afb4e0db3ff2480364286f230f8b91</id>
<content type='text'>
Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2
platforms.

Signed-off-by: Suneel Garapati &lt;sgarapati@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>treewide: convert devfdt_get_addr_ptr() to dev_read_addr_ptr()</title>
<updated>2020-08-22T14:53:37Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2020-08-04T05:14:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=702e57e113d85fef60ebe9e5c87194414666cfac'/>
<id>urn:sha1:702e57e113d85fef60ebe9e5c87194414666cfac</id>
<content type='text'>
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To help this tedious work, this commit converts devfdt_get_addr_ptr()
to dev_read_addr_ptr() by coccinelle. I also removed redundant casts
because dev_read_addr_ptr() returns an opaque pointer.

To generate this commit, I ran the following semantic patch
excluding include/dm/.

  &lt;smpl&gt;
  @@
  type T;
  expression dev;
  @@
  -(T *)devfdt_get_addr_ptr(dev)
  +dev_read_addr_ptr(dev)
  @@
  expression dev;
  @@
  -devfdt_get_addr_ptr(dev)
  +dev_read_addr_ptr(dev)
  &lt;/smpl&gt;

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: core: Fix devfdt_get_addr_ptr return value</title>
<updated>2020-08-22T13:59:14Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovidiu.panait@windriver.com</email>
</author>
<published>2020-08-03T19:17:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3fe69d3764c3ca6f304c51faa6aae7a84f1fa56c'/>
<id>urn:sha1:3fe69d3764c3ca6f304c51faa6aae7a84f1fa56c</id>
<content type='text'>
According to the description of devfdt_get_addr_ptr, this function should
return NULL on failure, but currently it returns (void *)FDT_ADDR_T_NONE.

Fix this by making devfdt_get_addr_ptr return NULL on failure, as
described in the function comments. Also, update the drivers currently
checking (void *)FDT_ADDR_T_NONE to check for NULL.

Signed-off-by: Ovidiu Panait &lt;ovidiu.panait@windriver.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>watchdog: Add support for K3 RTI watchdog</title>
<updated>2020-08-11T04:48:27Z</updated>
<author>
<name>Jan Kiszka</name>
<email>jan.kiszka@siemens.com</email>
</author>
<published>2020-06-23T11:15:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d388f360edacf6292a5ee7a37474799a3fe9f2ac'/>
<id>urn:sha1:d388f360edacf6292a5ee7a37474799a3fe9f2ac</id>
<content type='text'>
This is based on the Linux kernel driver for the RTI watchdog.

To actually reset the system on an AM65x, it requires firmware running
on the R5 that accepts the NMI and issues the actual system reset via
TISCI. Kind of an iTCO, except that this watchdog hardware has support
for no-way-out, and only for that.

On the J721E, reset works without extra firmware help when routing the
RTI interrupt via the ESM.

Signed-off-by: Jan Kiszka &lt;jan.kiszka@siemens.com&gt;
</content>
</entry>
<entry>
<title>Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq</title>
<updated>2020-07-27T19:18:15Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2020-07-27T19:18:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8d1fc6fb89826efb6bbbedb57862496e18737877'/>
<id>urn:sha1:8d1fc6fb89826efb6bbbedb57862496e18737877</id>
<content type='text'>
- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a
- lx2-watchdog support
- layerscape: pci-endpoint support, spin table relocation fixes and
  cleanups
- fsl-crypto: RNG support and bug fixes
</content>
</entry>
<entry>
<title>Watchdog: introduce ARM SBSA watchdog driver</title>
<updated>2020-07-27T08:54:15Z</updated>
<author>
<name>Zhao Qiang</name>
<email>qiang.zhao@nxp.com</email>
</author>
<published>2020-07-10T08:55:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f27d73e941525cab15682f2aea1673f5f943a128'/>
<id>urn:sha1:f27d73e941525cab15682f2aea1673f5f943a128</id>
<content type='text'>
According to Server Base System Architecture (SBSA) specification,
the SBSA Generic Watchdog has two stage timeouts: the first signal
(WS0) is for alerting the system by interrupt, the second one (WS1) is a
real hardware reset.
More details about the hardware specification of this device:
ARM DEN0029B - Server Base System Architecture (SBSA)

This driver can operate ARM SBSA Generic Watchdog as a single stage
In the single stage mode, when the timeout is reached, your system
will be reset by WS1. The first signal (WS0) is ignored.

Signed-off-by: Zhao Qiang &lt;qiang.zhao@nxp.com&gt;
Signed-off-by: Biwen Li &lt;biwen.li@nxp.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
</feed>
