This patch add support for the Trizeps IV module (520Mhz).

Signed-off-by: Stefano Babic <sbabic@denx.de>

Signed-off-by: Jason Jin <Jason.jin@freescale.com>

o add drivers/sil680.c to support the Sil680 IDE-controller.
o drivers/Makefile: add sil680.o.

Signed-off-by: Gary Jennejohn <garyj@denx.de>

The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.

Here the details of this patch:

o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
  board-specific settings. As an example the sequoia board requires 0.
  Idea from Stefan Roese <sr@denx.de>.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
  PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
  CFG_PCI_CACHE_LINE_SIZE to 0.

Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

This reverts commit 9468e680.
Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>

<ed.swarthout@freescale.com>

The problem is pciauto_setup_device() getting called from fsl_pci_init.c
is allocating memory space it doesn't need.

Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

The logic to check if there is a correct MAC address in the DM9000
EEPROM, added in the last patch, is wrong. Now the MAC address is
always taken from the environment, even if a suitable MAC is present
in the EEPROM.

Signed-off-by: Stefano Babic <sbabic@denx.de>

Fix the following warnings:
- usb.c:xx: warning: function declaration isn't a prototype
- usb_ohci.c:xxx: warning: passing argument 1 of '__fswab32' makes integer
  from pointer wihtout a cast

Signed-off-by: Martin Krause <martin.krase@tqs.de>

CPU physical address space was being wasted by allocating a
PCSRBAR PCI inbound region to it's memory space.

As a rule, PCSRBAR should be left alone since it does not affect
transactions from self and other masters may have changed it.

Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>