It can be optimised out by the compiler otherwise resulting
in obscure errors like a board not booting.

This has been documented in README since 2006 when these were
first fixed up for GCC 4.x.

Signed-off-by: John Rigby <john.rigby@linaro.org>

Fix some additional places.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-By: Albert ARIBAUD <albert.aribaud@free.fr>

The current code use all the voltage range support by the host
controller to do the validation.  This will cause problem when
the host supports Low Voltage Range.  Change the validation
voltage to be based on board setup.

Signed-off-by: Li Yang <leoli@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The max clock of MMC is 52MHz

Signed-off-by: Jerry Huang <Changm-Ming.Huang@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.

Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Fix clock divider for COM57H5M10XRC display.
The previous setting caused flicker.

Tested on Qong (EVBLite with COM57H5M10XRC).

Signed-off-by: Stefano Babic <sbabic@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>

eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.

Signed-off-by: P.V.Suresh <pala@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

According to Freescale reference manuals (eg section "13.4.4.2
Programming the UPMs" of the P4080 Reference Manual):

"Since the result of any update to the MxMR/MDR register must be in
effect before the dummy read or write to the UPM region, a write to
MxMR/MDR should be followed immediately by a read of MxMR/MDR."

The UPM on a custom P4080-based board did not work without performing
a read of MxMR/MDR after a write.

Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The following commit:

commit 46e91674fb4b6d06c6a4984c0b5ac7d9a16923f4
Author: Peter Tyser <ptyser@xes-inc.com>
Date:   Tue Nov 3 17:52:07 2009 -0600

    tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode

Removed setting Auto-Neg by default, however this is believed to be
proper default configuration for initialization of the TBI interface.

Instead we explicitly set CONFIG_TSEC_TBICR_SETTINGS for the
XPedite5370 & XPedite5500 boards that use a Broadcomm PHY which require
Auto-Neg to be disabled to function properly.

This addresses a breakage on the P2020 DS & MPC8572 DS boards when used
with an SGMII riser card.  We also remove setting
CONFIG_TSEC_TBICR_SETTINGS on the P1_P2_RDB family of boards as now the
default setting is sufficient for them.

Additionally, we clean up the code a bit to remove an unnecessary second
define.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Peter Tyser <ptyser@xes-inc.com>