u-boot.git/drivers, branch v2012.10-rc2

remove unnecessary code in ata_piix

2012-09-28T17:40:30+00:00

We set sata_curr_device to 0 right after returning from init_sata(), so there's
no point in setting it to the last scanned driver at this point.
Note: there are more duplicities with cmd_sata, but those might be required,
as the code seems to reset the entire controller on every scan, ignoring the
requested port number.

Signed-off-by: Pavel Herrmann

Merge branch 'master' of git://git.denx.de/u-boot-net

2012-09-27T19:06:07+00:00

SPL: SPI: Enhance spi_spl_load to match the other load functions

2012-09-27T18:20:27+00:00

Signed-off-by: Tom Rini

ARM: SPL: Convert davinci to CONFIG_SPL_FRAMEWORK

2012-09-27T18:20:10+00:00

- Convert the non-relocation part of board_init_f to spl_board_init, turn on CONFIG_SPL_BOARD_INIT in the configs.
- Remove duplicated code.
- Add spl_boot_device() that returns the statically chosen boot device.

Signed-off-by: Tom Rini

FEC: Replace magic contants

2012-09-27T17:22:10+00:00

Replace the magic contant 1 << 24 with properly defined bits.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Fabio Estevam 
Cc: Otavio Salvador 
Cc: Stefano Babic

FEC: Rework the TX wait mechanism

2012-09-27T17:22:10+00:00

The mechanism waiting for transmission to finish in fec_send() now
relies on the E-bit being cleared in the TX buffer descriptor. In
case of data cache being on, this means invalidation of data cache
above this TX buffer descriptor on each test for the E-bit being
cleared.

Apparently, there is another way to check if the transmission did
complete. This is by checking the TDAR bit in the X_DES_ACTIVE
register. Reading a register does not need any data cache invalidation,
which is beneficial.

Rework the sequence that wait for completion of the transmission so that
the TDAR bit is tested first and afterwards check the E-bit being clear.
This cuts down the number of cache invalidation calls to one.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Fabio Estevam 
Cc: Otavio Salvador 
Cc: Stefano Babic

FEC: Remove endless loop in the FEC driver

2012-09-27T17:22:09+00:00

The FEC hardware sometimes errors out on data transfer and hangs in
the tightloop adjusted by this patch. So add timeout into the tightloop
to make such a hang recoverable.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Fabio Estevam 
Cc: Otavio Salvador 
Cc: Stefano Babic

FEC: Properly align address over the buffers for cache ops

2012-09-27T17:22:09+00:00

Align the address that's to be invalidated/flushed properly.

Signed-off-by: Marek Vasut 
Cc: Benoit Thebaudeau 
Cc: Eric Nelson 
Cc: Fabio Estevam 
Cc: Joe Hershberger

FEC: Do not pass unaligned buffer to network stack

2012-09-27T17:22:09+00:00

Do not pass unaligned RX buffer to the upper layers. The upper layer,
especially in the ARP case, recycles the buffer and passes it back into
the FEC, into it's TX path. With caches enabled, the FEC hangs on this
from time to time.

Signed-off-by: Marek Vasut 
Cc: Benoit Thebaudeau 
Cc: Eric Nelson 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Tested-by: Fabio Estevam

net: Add Vitesse VSC8662 PHY support

2012-09-27T17:21:59+00:00

-VSC8662 is Dual Port 10/100/1000Base-T Phy,
 100Base-FX/1000/Base-X Gigabit Ethernt Transceiver Phy.

-Its register set and features are similar to
 other Vitesse Phys

Signed-off-by: Priyanka Jain 
Signed-off-by: York Sun