u-boot.git/drivers, branch v2014.10-rc1 Unnamed repository; edit this file 'description' to name the repository. Change Andy Fleming's email address 2014-08-06T13:12:30+00:00 Andy Fleming afleming@gmail.com 2014-07-25T22:39:08+00:00 b21f87a3e02461c600f1c172b053f1530a532d90 Messages to afleming@freescale.com now bounce, and should be directed to my personal address at afleming@gmail.com Signed-off-by: Andy Fleming <afleming@gmail.com> 
Messages to afleming@freescale.com now bounce, and should be
directed to my personal address at afleming@gmail.com

Signed-off-by: Andy Fleming <afleming@gmail.com>
Merge branch 'master' of git://git.denx.de/u-boot-spi 2014-08-06T12:38:19+00:00 Tom Rini trini@ti.com 2014-08-05T21:16:16+00:00 336450f5fc1c0d6eb0d95c536dadf0cc07466a4d 






spi, spi_mxc: do not hang in spi_xchg_single
2014-08-05T18:48:01+00:00

Heiko Schocher
hs@denx.de

2014-07-14T08:22:11+00:00

f659b57361c4a351ef2a5fc23b9197428e2e67f0

if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
endless loops. Add a timeout here to prevent endless hang.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Dirk Behme <dirk.behme@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>





if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
endless loops. Add a timeout here to prevent endless hang.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Dirk Behme <dirk.behme@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>







spi: Support half-duplex mode in FDT decode
2014-08-05T18:48:01+00:00

Simon Glass
sjg@chromium.org

2014-07-07T16:16:39+00:00

22052c6236cbebc446ffd51ac69271fe063c654a

This parameter should also be supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>





This parameter should also be supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>







exynos: spi: Fix calculation of SPI transaction start time
2014-08-05T18:48:01+00:00

Simon Glass
sjg@chromium.org

2014-07-07T16:16:38+00:00

a4e29db2571144a05ad09380b3674fe5b492f693

The SPI transaction delay is supposed to be measured from the end of one
transaction to the start of the next. The code does not work that way, so
fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>





The SPI transaction delay is supposed to be measured from the end of one
transaction to the start of the next. The code does not work that way, so
fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>







cros_ec: Fix two bugs in the SPI implementation
2014-08-05T18:48:01+00:00

Simon Glass
sjg@chromium.org

2014-07-07T16:16:37+00:00

2001b9a64165658e14f5afbe16874e0c55ddd04f

An incorrect message version is passed to the EC in some cases and the
parameters of one function are switched.

Fix these problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>





An incorrect message version is passed to the EC in some cases and the
parameters of one function are switched.

Fix these problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>







sf: sf_ops: Stop leaking memory
2014-08-05T18:48:01+00:00

Marek Vasut
marex@denx.de

2014-07-12T12:41:31+00:00

a52a178f0b4dce6a85a45ccea348be92fc7f1b6d

It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>





It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>







MMC: atmel_mci: enable high speed mode support
2014-08-01T17:01:33+00:00

Bo Shen
voice.shen@atmel.com

2014-07-31T06:39:32+00:00

da55c66ec92c962435175cf0b4f4d61732ca3ebf

If the MCI IP version >= 0x300, it supports hight speed mode
option, this patch enable it.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>





If the MCI IP version >= 0x300, it supports hight speed mode
option, this patch enable it.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>







MMC: atmel_mci: refactor setting the mode register
2014-08-01T17:01:09+00:00

Bo Shen
voice.shen@atmel.com

2014-07-31T06:39:30+00:00

cd60ebd430ab0aa5e2ed6afeb28c1ed4b2d01388

The mode register is different between MCI IP version.
So, according to MCI IP version to set the mode register.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>





The mode register is different between MCI IP version.
So, according to MCI IP version to set the mode register.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>







mmc/dw_mmc: Fix clock divider calculation error for bypass mode
2014-08-01T16:45:32+00:00

Chin Liang See
clsee@altera.com

2014-06-10T06:26:52+00:00

6ace153d130f528b88117b1edcfe017ea1852d67

To fix the clock divider calculation error when the controller
clock same as the operating frequency. This is known as bypass
mode. In this mode, the divider should be 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>





To fix the clock divider calculation error when the controller
clock same as the operating frequency. This is known as bypass
mode. In this mode, the divider should be 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>