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<title>u-boot.git/drivers, branch v2015.10-rc5</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>nand: omap_gpmc: Change correctable bit-flips messages to debug()</title>
<updated>2015-10-11T21:12:13+00:00</updated>
<author>
<name>Ezequiel García</name>
<email>ezequiel@vanguardiasur.com.ar</email>
</author>
<published>2015-10-04T21:34:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d1d0167663ada7c8fdb4d9d50d3fe132ac5a8b5e'/>
<id>d1d0167663ada7c8fdb4d9d50d3fe132ac5a8b5e</id>
<content type='text'>
Messages on corrected bit-flips are not really useful,
as bit-flips are perfectly normal. Let's avoid cluttering
the console and make them debug.

Signed-off-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
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<pre>
Messages on corrected bit-flips are not really useful,
as bit-flips are perfectly normal. Let's avoid cluttering
the console and make them debug.

Signed-off-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
</pre>
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</content>
</entry>
<entry>
<title>Revert "powerpc: ppc4xx: remove lwmon5 support"</title>
<updated>2015-10-11T21:12:09+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2015-10-02T06:20:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=04386f656bbc35abd7718a4bbbba7fcfb4f59aef'/>
<id>04386f656bbc35abd7718a4bbbba7fcfb4f59aef</id>
<content type='text'>
This reverts commit 8fe11b8901a31d11990488c82bc23612589d57be.

I'll add support to lwmon5 in the next patch and will remove
support for the broken lcd4_lwmon5 as well.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
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<pre>
This reverts commit 8fe11b8901a31d11990488c82bc23612589d57be.

I'll add support to lwmon5 in the next patch and will remove
support for the broken lcd4_lwmon5 as well.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>mtd: sf: Add support AT26DF081A chip</title>
<updated>2015-10-11T11:13:06+00:00</updated>
<author>
<name>Yao Yuan</name>
<email>yao.yuan@freescale.com</email>
</author>
<published>2015-09-15T10:28:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f2b76c6037f8d2f54e938f42ad9ef01488c11425'/>
<id>f2b76c6037f8d2f54e938f42ad9ef01488c11425</id>
<content type='text'>
AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card.
We can access the flash through DSPI2 on LS1021ATWR board.

Signed-off-by: Yuan Yao &lt;yao.yuan@freescale.com&gt;
Reviewed-by: Jagan Teki &lt;jteki@openedev.com&gt;
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<pre>
AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card.
We can access the flash through DSPI2 on LS1021ATWR board.

Signed-off-by: Yuan Yao &lt;yao.yuan@freescale.com&gt;
Reviewed-by: Jagan Teki &lt;jteki@openedev.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>spi: tegra20: Add support for mode selection</title>
<updated>2015-10-11T11:13:06+00:00</updated>
<author>
<name>Mirza Krak</name>
<email>mirza.krak@hostmobility.com</email>
</author>
<published>2015-09-08T08:30:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5cb1b7b395c0150e179f3b748d755cdc2f613a06'/>
<id>5cb1b7b395c0150e179f3b748d755cdc2f613a06</id>
<content type='text'>
Respect the mode passed in set_mode ops.

Signed-off-by: Mirza Krak &lt;mirza.krak@hostmobility.com&gt;
Reviewed-by: Jagan Teki &lt;jteki@openedev.com&gt;
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<pre>
Respect the mode passed in set_mode ops.

Signed-off-by: Mirza Krak &lt;mirza.krak@hostmobility.com&gt;
Reviewed-by: Jagan Teki &lt;jteki@openedev.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>spi: zynq_spi: Fix to configure CPOL, CPHA mask</title>
<updated>2015-10-11T11:13:06+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jteki@openedev.com</email>
</author>
<published>2015-09-07T20:08:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a22bba81e40959c3675b794422508911034049d4'/>
<id>a22bba81e40959c3675b794422508911034049d4</id>
<content type='text'>
priv-&gt;mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv-&gt;mode is invalid hence use
mode from .set_speed argument, and at the end
priv-&gt;mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki &lt;jteki@openedev.com&gt;
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<pre>
priv-&gt;mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv-&gt;mode is invalid hence use
mode from .set_speed argument, and at the end
priv-&gt;mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki &lt;jteki@openedev.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>spi: xilinx_spi: Fix to configure CPOL, CPHA mask</title>
<updated>2015-10-11T11:13:06+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jteki@openedev.com</email>
</author>
<published>2015-09-07T19:56:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d5f60737dbaac82f3f7d49eb03ece443beb70fc8'/>
<id>d5f60737dbaac82f3f7d49eb03ece443beb70fc8</id>
<content type='text'>
priv-&gt;mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv-&gt;mode is invalid hence use
mode from .set_speed argument, and at the end
priv-&gt;mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki &lt;jteki@openedev.com&gt;
</content>
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<pre>
priv-&gt;mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv-&gt;mode is invalid hence use
mode from .set_speed argument, and at the end
priv-&gt;mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki &lt;jteki@openedev.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-x86</title>
<updated>2015-10-09T13:55:33+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2015-10-09T13:55:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=38ab75a2aa54b97429b2f33ff5d3c7ddcabf1456'/>
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<pre>
</pre>
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</entry>
<entry>
<title>pci: Fix expansion ROM programming for multi-function devices</title>
<updated>2015-10-08T18:09:09+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-10-07T09:13:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7445435fb32824e0cfd05beb7013be8f84e9ee09'/>
<id>7445435fb32824e0cfd05beb7013be8f84e9ee09</id>
<content type='text'>
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator
for multi-function devices. We should mask it off before using
it as the header type.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator
for multi-function devices. We should mask it off before using
it as the header type.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-dm</title>
<updated>2015-10-08T07:03:41+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2015-10-08T07:03:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=739c5e08335b15ac7c55c98ada32eb97ba508a5f'/>
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<pre>
</pre>
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</entry>
<entry>
<title>sandbox: Correct operaion of 'reset' command</title>
<updated>2015-10-05T14:47:49+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-10-03T17:21:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7bb91dd109e2aff5f7f51aed44ac7890f9a4d158'/>
<id>7bb91dd109e2aff5f7f51aed44ac7890f9a4d158</id>
<content type='text'>
Currently 'reset' only works with the test device tree. When run without a
device tree, or with the normal device tree, the following error is
displayed:

   Reset not supported on this platform

Fix the driver and the standard device tree to avoid this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reported-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Tested-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
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<pre>
Currently 'reset' only works with the test device tree. When run without a
device tree, or with the normal device tree, the following error is
displayed:

   Reset not supported on this platform

Fix the driver and the standard device tree to avoid this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reported-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Tested-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
</pre>
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</content>
</entry>
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