In struct e1000_rx_desc, field 'length' is declared as
uint16_t, so use le16_to_cpu() to do endianness conversion.

Also drop conversion on 'status' which is declared as
uint8_t.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Table 41 of the JEDEC standard for eMMC says that bit 31 of
the command argument is obsolete when issuing the ERASE
command (CMD38) on page 115 of this document:
	http://www.jedec.org/sites/default/files/docs/jesd84-B45.pdf

The SD Card Association Physical Layer Simplified Specification also
makes no mention of the use of bit 31.
	https://www.sdcard.org/downloads/pls/part1_410.pdf

The Linux kernel distinguishes between secure (bit 31 set) and
non-secure erase, and this patch copies the macro names from
include/linux/mmc/core.h.

Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Eric Nelson <eric@nelint.com>
Tested-by: Hector Palacios <hector.palacios@digi.com>

drivers/mtd/ubi/io.c:1354:3: error: 'dump_len' undeclared (first use in
this function)
   dump_len = max_t(int, 128, len - i);

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

This could avoid executing the code that only applies to i.MX platforms.

The bus_i2c_init() is called before relocation and will assgin value
to a static variable. If U-Boot is then still running in a flash
device, it's theoretically not allowed to write data to flash without
an erasing operation. For i.MX platforms, the U-Boot is always running
in DDR.

Actually it causes asynchronous error when the ARM64 system error
report is enabled and the flash write protect is set.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

If fecmxc_initialize_multi() fails, it frees but does not unregister
the mdio bus, causing subsequent uses of the "mii" command to crash.
Fix this by adding mdio_unregister() calls where needed.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Reviewed-by: Eric Nelson <eric@nelint.com>

If the host clock frequency is higher than 100 MHz, the MDIO hold
time needs to be increased from its current setting of one cycle in
order to meet the specified minium of 10 ns.  Writing an appropriate
value to the HOLDTIME field of the MII_SPEED register achieves this.

Comment copied from Linux kernel.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Reviewed-by: Eric Nelson <eric@nelint.com>

This patch writes the default values for TXTL and RXTL to UARTx_UFCR.
Without this patch some older kernel versions crash as UARTx_UFCR was
not always correctly initialized.

Signed-off-by: Maximilian Schwerin <maximilian.schwerin@tigris.de>

The low four bits of the SYSCTL register are reserved on the USDHC
controller on i.MX6 and i.MX7 processors, but are used for clocking
operations on earlier models.

Guard against their usage by hiding the bit mask macros on those
processors.

These bits are used to prevent glitches when changing clocks on
i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7.

>From the i.MX6DQ RM:
	To prevent possible glitch on the card clock, clear the
	FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS
	or DVS in System Control Register) or setting RSTA bit.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Hector Palacios <hector.palacios@digi.com>