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<title>u-boot.git/drivers, branch v2016.03-rc1</title>
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<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-atmel</title>
<updated>2016-02-02T12:24:52+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-02-02T12:24:52+00:00</published>
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<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2016-02-02T11:51:05+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-02-02T11:51:05+00:00</published>
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<entry>
<title>atmel_nand: Add 32 bit ecc support for sama5d2 chip</title>
<updated>2016-02-02T10:49:11+00:00</updated>
<author>
<name>Josh Wu</name>
<email>josh.wu@atmel.com</email>
</author>
<published>2015-11-24T08:34:01+00:00</published>
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Also if minimum ecc requirment is bigger then what we support, then just
use our maxium pmecc support.
But it is not safe, so we'll output a warning about this.

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
Reviewed-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
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<pre>
Also if minimum ecc requirment is bigger then what we support, then just
use our maxium pmecc support.
But it is not safe, so we'll output a warning about this.

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
Reviewed-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
</pre>
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</entry>
<entry>
<title>atmel_nand_ecc: update pmecc registers according to sama5d2 chip</title>
<updated>2016-02-02T10:49:10+00:00</updated>
<author>
<name>Josh Wu</name>
<email>josh.wu@atmel.com</email>
</author>
<published>2015-11-24T08:34:00+00:00</published>
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1. add the pmecc register mapping for sama5d2.
2. add the pmecc error location register mapping for sama5d2.
3. add some new field that is different from old ip.
4. add sama5d2 pmecc ip version number.

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
Reviewed-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
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1. add the pmecc register mapping for sama5d2.
2. add the pmecc error location register mapping for sama5d2.
3. add some new field that is different from old ip.
4. add sama5d2 pmecc ip version number.

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
Reviewed-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
</pre>
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<entry>
<title>drivers: net: Add ethernet driver for Microchip PIC32.</title>
<updated>2016-02-01T21:14:02+00:00</updated>
<author>
<name>Purna Chandra Mandal</name>
<email>purna.mandal@microchip.com</email>
</author>
<published>2016-01-28T10:00:21+00:00</published>
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<id>23e7578c9b17a5af8804ee2df8e52b9324651b6d</id>
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This driver implements MAC and MII layer of the ethernet controller.
Network data transfer is handled by controller internal DMA engine.
Ethernet controller is configurable through device-tree file.

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
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This driver implements MAC and MII layer of the ethernet controller.
Network data transfer is handled by controller internal DMA engine.
Ethernet controller is configurable through device-tree file.

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
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<entry>
<title>drivers: net: phy: add SMSC LAN8740 Phy support.</title>
<updated>2016-02-01T21:14:02+00:00</updated>
<author>
<name>Purna Chandra Mandal</name>
<email>purna.mandal@microchip.com</email>
</author>
<published>2016-01-28T10:00:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=46c9d938ca9d603fb5bf4ed8443d51c5b283fc89'/>
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Add SMSC LAN8740 Phy support required for PIC32MZDA devices.

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
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Add SMSC LAN8740 Phy support required for PIC32MZDA devices.

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</pre>
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</entry>
<entry>
<title>drivers: mmc: add driver for Microchip PIC32 SDHCI controller.</title>
<updated>2016-02-01T21:14:01+00:00</updated>
<author>
<name>Andrei Pistirica</name>
<email>andrei.pistirica@microchip.com</email>
</author>
<published>2016-01-28T10:00:18+00:00</published>
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This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.

Signed-off-by: Andrei Pistirica &lt;andrei.pistirica@microchip.com&gt;
Signed-off-by: Sandeep Sheriker Mallikarjun &lt;sandeepsheriker.mallikarjun@microchip.com&gt;
Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
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This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.

Signed-off-by: Andrei Pistirica &lt;andrei.pistirica@microchip.com&gt;
Signed-off-by: Sandeep Sheriker Mallikarjun &lt;sandeepsheriker.mallikarjun@microchip.com&gt;
Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
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<entry>
<title>drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.</title>
<updated>2016-02-01T21:14:01+00:00</updated>
<author>
<name>Purna Chandra Mandal</name>
<email>purna.mandal@microchip.com</email>
</author>
<published>2016-01-28T10:00:15+00:00</published>
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<id>9ffa7a35ef940b27813c11f68eb28a6b82696915</id>
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This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker &lt;paul.thacker@microchip.com&gt;
Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker &lt;paul.thacker@microchip.com&gt;
Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</entry>
<entry>
<title>drivers: serial: add driver for Microchip PIC32 UART controller.</title>
<updated>2016-02-01T21:14:00+00:00</updated>
<author>
<name>Paul Thacker</name>
<email>paul.thacker@microchip.com</email>
</author>
<published>2016-01-28T10:00:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9e160ee823b44e0a63bc469d42d7d9fcab54b60b'/>
<id>9e160ee823b44e0a63bc469d42d7d9fcab54b60b</id>
<content type='text'>
This adds PIC32 UART controller support based on driver model.

Signed-off-by: Paul Thacker &lt;paul.thacker@microchip.com&gt;
Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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This adds PIC32 UART controller support based on driver model.

Signed-off-by: Paul Thacker &lt;paul.thacker@microchip.com&gt;
Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</entry>
<entry>
<title>drivers: gpio: add driver for Microchip PIC32 GPIO controller.</title>
<updated>2016-02-01T21:14:00+00:00</updated>
<author>
<name>Purna Chandra Mandal</name>
<email>purna.mandal@microchip.com</email>
</author>
<published>2016-01-28T10:00:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=386d934e0b2dbe64d4b156eb64b819bdd5c7c121'/>
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In PIC32 GPIO controller is part of PIC32 pin controller.
PIC32 has ten independently programmable ports and each with multiple pins.
Each of these pins can be configured and used as GPIO, provided they
are not in use for other peripherals.

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
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In PIC32 GPIO controller is part of PIC32 pin controller.
PIC32 has ten independently programmable ports and each with multiple pins.
Each of these pins can be configured and used as GPIO, provided they
are not in use for other peripherals.

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
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