According to the TRM you have to set bits [21:20] to 0b10 for RAW mode, so
(0x10 << 20) is obviously wrong here.

Signed-off-by: Martin Pietryka <martin.pietryka@chello.at>

The terminal condition in the area where a PCI device is scanned is wrong,
and 1f.7 isn't scanned.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

This allows to drop annoying (char *) casts when setting the host
name of struct sdhci_host.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

get_timer() returns an unsigned 64-bit value, but is currently assigned to
a signed 32-bit variable. Due to sign extension and data truncation, this
causes the timeout loop in spi_flash_cmd_wait_ready() to immediately (and
incorrectly) fire for about 50% of all time values, based on whether bit
31 is set. In sandbox at least, this causes the test to pass or fail based
on system uptime, as opposed to time since the U-Boot binary was started.

Fixes: 4efad20a1751 ("sf: Update status reg check in spi_flash_cmd_wait_ready")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

U-Boot typically interprets unprefixed numbers as base 16, and DFU RAM
entity parsing has historically done so. Reverse the change to default
to base 10, so that values in previously working command-lines aren't
mis-parsed, causing RAM corruption, crashes, hangs, etc.

Fixes: 6aeb877afef0 ("drivers: dfu: ram: fix a crash with dfu ram with invalid dfu_alt_info env")

Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
[Test HW: AM335x BBB]

U-Boot crashes when an invalid dfu_alt_info is set and tried
using dfu command. Fixing this as it is handled in dfu-mmc.

=> dfu 0 ram 0
data abort
pc : [<9ff893d6>]          lr : [<9ff6edb9>]
reloc pc : [<808323d6>]    lr : [<80817db9>]
sp : 9ef36cf0  ip : 00000158     fp : 9ffbc0b8
r10: 9ffbc0b8  r9 : 9ef36ed8     r8 : 00000000
r7 : 00000000  r6 : 9ffbc0c8     r5 : 9ef36cfc  r4 : 9ef392c8
r3 : 00000004  r2 : 00000000     r1 : 9ff9a985  r0 : ffffffff
Flags: Nzcv  IRQs off  FIQs on  Mode SVC_32
Resetting CPU ...

resetting ...

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>