u-boot.git/drivers, branch v2017.01-rc1 Unnamed repository; edit this file 'description' to name the repository. Merge git://git.denx.de/u-boot-fsl-qoriq 2016-12-05T22:00:23+00:00 Tom Rini trini@konsulko.com 2016-12-05T22:00:23+00:00 bf50ac918bfbc0042e43b0a5c87cfa9dd4351e0a 






fsl/usb: enable the errata-a005697 for ls1012a
2016-12-05T16:31:45+00:00

jerry.huang@nxp.com
jerry.huang@nxp.com

2016-12-01T03:44:25+00:00

8545c5415f489caafc2e686dd43eaffc9228c460

Enable the errata-a005697 for ls1012a

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>





Enable the errata-a005697 for ls1012a

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>







fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum
2016-12-05T16:31:45+00:00

Shengzhou Liu
Shengzhou.Liu@nxp.com

2016-11-21T03:36:48+00:00

02fb2761576be8096ebf1b3f961a2cdb21b422ae

- add additional function erratum_a009942_check_cpo to check if the
  board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
  fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>





- add additional function erratum_a009942_check_cpo to check if the
  board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
  fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>







fsl/ddr: Fix compiling warning
2016-12-05T16:31:45+00:00

Shengzhou Liu
Shengzhou.Liu@nxp.com

2016-11-21T03:36:47+00:00

5a17b8b5dab8973089b7400d05f8503d56f29370

Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>





Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>







Merge git://www.denx.de/git/u-boot-i2c
2016-12-05T16:02:01+00:00

Tom Rini
trini@konsulko.com

2016-12-05T16:02:01+00:00

ea43683b1381c9bfa7ad1c3238c4f1f3328882db












sata: sata_mv: Fix misaligned cache warnings
2016-12-05T12:53:42+00:00

Stefan Roese
sr@denx.de

2016-11-18T16:21:51+00:00

5102af4d2f53ec8d76ce60d103c65ae062b9c8fe

This patch fixes the warnings about misaligned cache on Armada XP:

CACHE: Misaligned operation at range [7facb400, 7facb460]

Signed-off-by: Stefan Roese <sr@denx.de>





This patch fixes the warnings about misaligned cache on Armada XP:

CACHE: Misaligned operation at range [7facb400, 7facb460]

Signed-off-by: Stefan Roese <sr@denx.de>







pci: mvebu: Add PCIe driver for Armada-8K
2016-12-05T12:34:33+00:00

Shadi Ammouri
shadi@marvell.com

2016-10-27T11:29:41+00:00

182ba1a7dfe94fed21eff666cc1a4f38c7a3e88e

This patch adds a driver for the PCIe controller integrated in the
Marvell Armada-8K SoC. This controller is based on the DesignWare
IP core.

The original version was written by Shadi and Yehuda. I ported this
driver to the latest mainline U-Boot version with DM support.

Tested on the Marvell DB-88F8040 Armada-8K eval board.

Signed-off-by: Shadi Ammouri <shadi@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>





This patch adds a driver for the PCIe controller integrated in the
Marvell Armada-8K SoC. This controller is based on the DesignWare
IP core.

The original version was written by Shadi and Yehuda. I ported this
driver to the latest mainline U-Boot version with DM support.

Tested on the Marvell DB-88F8040 Armada-8K eval board.

Signed-off-by: Shadi Ammouri <shadi@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>







drivers/phy: marvell: Add support for the slave CP COMPHY device
2016-12-05T12:28:23+00:00

Stefan Roese
sr@denx.de

2016-10-25T16:16:25+00:00

e8c3156e8da94bd8ee651385cdd76bb7f842731e

With the support for the Armada 8k, a 2nd COMPHY controller now needs
to get supported from the CP110 slave controller. This patch adds support
for this 2nd contoller in the COMPHY driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>





With the support for the Armada 8k, a 2nd COMPHY controller now needs
to get supported from the CP110 slave controller. This patch adds support
for this 2nd contoller in the COMPHY driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>







dm: i2c: Add a note to I2C drivers which need conversion
2016-12-05T12:28:03+00:00

Simon Glass
sjg@chromium.org

2016-11-23T13:34:44+00:00

2852709676c89e45b564ff0d64ce53e921c99c1d

Maintainers need to be notified more directly of the need to convert these
drivers. Add a note to the top each affected file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>





Maintainers need to be notified more directly of the need to convert these
drivers. Add a note to the top each affected file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>







samsung: i2c: Split the high-speed I2C code into a new driver
2016-12-05T12:27:54+00:00

Simon Glass
sjg@chromium.org

2016-11-23T13:34:43+00:00

37b8eb37f8950538425d9956b65e8911a986002b

Now that driver model is used for I2C on all boards, we can split the
high-speed code into its own driver. There is virtually no common code,
and this significantly reduces confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>





Now that driver model is used for I2C on all boards, we can split the
high-speed code into its own driver. There is virtually no common code,
and this significantly reduces confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>