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<title>u-boot.git/drivers, branch v2018.05-rc1</title>
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<entry>
<title>Merge git://git.denx.de/u-boot-dm</title>
<updated>2018-04-02T00:36:39+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-04-02T00:36:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0e5d3e311189ca07aa7b5802deaff9861fc33574'/>
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<entry>
<title>core: ofnode: Fix translation for #size-cells == 0</title>
<updated>2018-04-01T14:19:10+00:00</updated>
<author>
<name>Mario Six</name>
<email>mario.six@gdsys.cc</email>
</author>
<published>2018-03-12T13:53:33+00:00</published>
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Commit 286ede6 ("drivers: core: Add translation in live tree case") made
dev_get_addr always use proper bus translations for addresses read from
the device tree. But this leads to problems with certain busses, e.g.
I2C busses, which run into an error during translation, and hence stop
working.

It turns out that of_translate_address() and fdt_translate_address()
stop the address translation with an error when they're asked to
translate addresses for busses where #size-cells == 0 (comment from
drivers/core/of_addr.c):

 * Note: We consider that crossing any level with #size-cells == 0 to mean
 * that translation is impossible (that is we are not dealing with a value
 * that can be mapped to a cpu physical address). This is not really specified
 * that way, but this is traditionally the way IBM at least do things

To fix this case, we check in both the live-tree and non-live tree-case,
whether the bus of the device whose address is about to be translated
has size-cell size zero. If this is the case, we just read the address
as a plain integer and return it, and only apply bus translations if the
size-cell size if greater than zero.

Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
Signed-off-by: Martin Fuzzey &lt;mfuzzey@parkeon.com&gt;
Reported-by: Martin Fuzzey &lt;mfuzzey@parkeon.com&gt;
Fixes: 286ede6 ("drivers: core: Add translation in live tree case")
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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Commit 286ede6 ("drivers: core: Add translation in live tree case") made
dev_get_addr always use proper bus translations for addresses read from
the device tree. But this leads to problems with certain busses, e.g.
I2C busses, which run into an error during translation, and hence stop
working.

It turns out that of_translate_address() and fdt_translate_address()
stop the address translation with an error when they're asked to
translate addresses for busses where #size-cells == 0 (comment from
drivers/core/of_addr.c):

 * Note: We consider that crossing any level with #size-cells == 0 to mean
 * that translation is impossible (that is we are not dealing with a value
 * that can be mapped to a cpu physical address). This is not really specified
 * that way, but this is traditionally the way IBM at least do things

To fix this case, we check in both the live-tree and non-live tree-case,
whether the bus of the device whose address is about to be translated
has size-cell size zero. If this is the case, we just read the address
as a plain integer and return it, and only apply bus translations if the
size-cell size if greater than zero.

Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
Signed-off-by: Martin Fuzzey &lt;mfuzzey@parkeon.com&gt;
Reported-by: Martin Fuzzey &lt;mfuzzey@parkeon.com&gt;
Fixes: 286ede6 ("drivers: core: Add translation in live tree case")
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</entry>
<entry>
<title>dm: core: make fixed-clock dt scan live dt compatible</title>
<updated>2018-04-01T14:15:11+00:00</updated>
<author>
<name>Andy Yan</name>
<email>andy.yan@rock-chips.com</email>
</author>
<published>2018-03-01T06:08:15+00:00</published>
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dm_scan_fdt_node can't work when live dt is active,
we should use dm_scan_fdt_live instead.

Signed-off-by: Andy Yan &lt;andy.yan@rock-chips.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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dm_scan_fdt_node can't work when live dt is active,
we should use dm_scan_fdt_live instead.

Signed-off-by: Andy Yan &lt;andy.yan@rock-chips.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</entry>
<entry>
<title>pinctrl-uclass: convert to use live dt</title>
<updated>2018-03-31T07:59:59+00:00</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2018-02-09T02:56:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1e656ad08c92c7b9db86bcc16eeb64fe5679f7c9'/>
<id>1e656ad08c92c7b9db86bcc16eeb64fe5679f7c9</id>
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Use live dt interface for pinctrl_select_state_full()

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
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Use live dt interface for pinctrl_select_state_full()

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</pre>
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</entry>
<entry>
<title>core: add uclass_get_device_by_phandle_id() api</title>
<updated>2018-03-31T07:59:59+00:00</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2018-02-09T02:56:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d255fade66414271950ab605098439591a67f1ed'/>
<id>d255fade66414271950ab605098439591a67f1ed</id>
<content type='text'>
Add api for who can not get phandle from a device property.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
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Add api for who can not get phandle from a device property.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</pre>
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</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-marvell</title>
<updated>2018-03-30T22:18:22+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-03-30T22:18:22+00:00</published>
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<entry>
<title>Merge git://git.denx.de/u-boot-x86</title>
<updated>2018-03-30T22:17:23+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-03-30T22:17:23+00:00</published>
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<entry>
<title>Merge git://git.denx.de/u-boot-riscv</title>
<updated>2018-03-30T22:16:56+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-03-30T22:16:56+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0ca0a546b186478b9de80cbd27fa8baf17e30863'/>
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<entry>
<title>arm64: a37xx: pci: add support for aardvark pcie driver</title>
<updated>2018-03-30T10:52:49+00:00</updated>
<author>
<name>Wilson Ding</name>
<email>dingwei@marvell.com</email>
</author>
<published>2018-03-26T07:57:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e51f2b14c4936daf3e3040bddb15f63d35e6d988'/>
<id>e51f2b14c4936daf3e3040bddb15f63d35e6d988</id>
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This patch introduced the Aardvark PCIe driver based
driver model.
The PCIe driver is supposed to work in Root Complex
mode. It only supports X1 lane width.

Signed-off-by: Wilson Ding &lt;dingwei@marvell.com&gt;
Reviewed-on: http://vgitil04.il.marvell.com:8080/38725
Reviewed-by: Victor Gu &lt;xigu@marvell.com&gt;
Reviewed-by: Hua Jing &lt;jinghua@marvell.com&gt;
Tested-by: Hua Jing &lt;jinghua@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
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This patch introduced the Aardvark PCIe driver based
driver model.
The PCIe driver is supposed to work in Root Complex
mode. It only supports X1 lane width.

Signed-off-by: Wilson Ding &lt;dingwei@marvell.com&gt;
Reviewed-on: http://vgitil04.il.marvell.com:8080/38725
Reviewed-by: Victor Gu &lt;xigu@marvell.com&gt;
Reviewed-by: Hua Jing &lt;jinghua@marvell.com&gt;
Tested-by: Hua Jing &lt;jinghua@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
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</entry>
<entry>
<title>arm64: a37xx: pinctrl: Correct mpp definitions</title>
<updated>2018-03-30T10:52:48+00:00</updated>
<author>
<name>Ken Ma</name>
<email>make@marvell.com</email>
</author>
<published>2018-03-26T07:56:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dc36235abe408cf450daa7b06d612084119dd841'/>
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This patch corrects below mpp definitions:
 - The sdio_sb group is composed of 6 pins and not 5;
 - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6];
 - Pin of group "pmic0" is mpp1[6] but not mpp1[16];
 - Pin of group "pmic1" is mpp1[7] but not mpp1[17];
 - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its
   bitmask is bit4;
 - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is
   bit5 | bit9 | bit10 but not bit4;
 - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to
   bit11 | bit12 | bit13.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43288
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Hua Jing &lt;jinghua@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
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This patch corrects below mpp definitions:
 - The sdio_sb group is composed of 6 pins and not 5;
 - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6];
 - Pin of group "pmic0" is mpp1[6] but not mpp1[16];
 - Pin of group "pmic1" is mpp1[7] but not mpp1[17];
 - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its
   bitmask is bit4;
 - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is
   bit5 | bit9 | bit10 but not bit4;
 - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to
   bit11 | bit12 | bit13.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43288
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Hua Jing &lt;jinghua@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
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