Make the initialization sequence consistent with the Linux kernel
driver.

Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>

This fixes sporadic timeout on initial packet Tx (usually ARP), with an
error message like:

  timeout: packet not sent

Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>

phyread can timeout and val will contain random value. Initialize it to
zero not to report random value in case of error.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

With the introduction of early timer support in the TSC driver,
the capability of getting clock rate from device tree was lost
unfortunately. Now we bring such functionality back, but with a
limitation that when TSC is used as early timer, specifying clock
rate from device tree does not work.

This fixes random boot failures seen on QEMU targets: printing "TSC
frequency is ZERO" and reset forever.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.

unfortunately these are fixed due to lack of separate
clock, reset drivers.

Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.

This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.

We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

For ohci, the maximam supported endpoint number is 32(in and out), and
now we have used (usb_pipeendpoint(pipe) << 1) to index the specified
endpoint descritor, usb_pipeendpoint(pipe) can reach 0xf, so we need
change the NUM_EDs from 8 to 32.

Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

ohci-hcd casts priv_data pointer to (ohci_t *), thus it must be
the first member in private data struct.

Fixes 831cc98b1 ("usb: sunxi: Simplify ccm reg base code")

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>