u-boot.git/drivers, branch v2020.01-rc1 Unnamed repository; edit this file 'description' to name the repository. Merge tag 'mmc-10-29-2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc 2019-10-30T13:06:33+00:00 Tom Rini trini@konsulko.com 2019-10-30T13:06:33+00:00 700336f7e4452f58ebe074e4acfd15d57bb6be84 - fsl_esdhc driver cleanup - spl_mmc bug fix to avoid access wrong emmc partition 
- fsl_esdhc driver cleanup
- spl_mmc bug fix to avoid access wrong emmc partition
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi 2019-10-30T13:04:52+00:00 Tom Rini trini@konsulko.com 2019-10-30T13:04:52+00:00 cc64810dc6234a3537502a05988fa7a1a6fa5d55 - H6 dts(i) sync (Clément) - H6 PIO (Icenowy) - Fix pll1 clock calculation (Stefan) - H6 dram, half DQ (Jernej) - A64 OLinuXino eMMC (Sunil) 
- H6 dts(i) sync (Clément)
- H6 PIO (Icenowy)
- Fix pll1 clock calculation (Stefan)
- H6 dram, half DQ (Jernej)
- A64 OLinuXino eMMC (Sunil)
mmc: fsl_esdhc: drop i.MX DDR support code 2019-10-29T02:09:22+00:00 Yangbo Lu yangbo.lu@nxp.com 2019-10-21T10:09:09+00:00 5d336d1701567e5025c3010b325e633a677c30a2 A previous patch below adding DDR mode support was actually for i.MX platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC, it uses different process for DDR mode, and hasn't been supported. Let's drop DDR support code for i.MX in fsl_esdhc driver. 0e1bf61 mmc: fsl_esdhc: Add support for DDR mode Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> 
A previous patch below adding DDR mode support was actually for i.MX
platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC,
it uses different process for DDR mode, and hasn't been supported.
Let's drop DDR support code for i.MX in fsl_esdhc driver.

0e1bf61 mmc: fsl_esdhc: Add support for DDR mode

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
mmc: fsl_esdhc: remove redundant DM_MMC checking 2019-10-29T02:09:21+00:00 Yangbo Lu yangbo.lu@nxp.com 2019-10-21T10:09:08+00:00 2913926f3b3dec282f8773e3c02377c9600d8267 Remove redundant DM_MMC checking which is already in DM_MMC conditional compile block. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> 
Remove redundant DM_MMC checking which is already in DM_MMC conditional
compile block.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC 2019-10-29T02:09:21+00:00 Yangbo Lu yangbo.lu@nxp.com 2019-10-21T10:09:07+00:00 41dec2fe99512e941261594f522b2e7d485c314b U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already support it, so let's force to use it. - Drop non-BLK support for DM_MMC introduced by below patch. 66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled - Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC). - Use DM_MMC instead of BLK for conditional compile. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> 
U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already
support it, so let's force to use it.

- Drop non-BLK support for DM_MMC introduced by below patch.
  66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled

- Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC).

- Use DM_MMC instead of BLK for conditional compile.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips 2019-10-26T00:07:24+00:00 Tom Rini trini@konsulko.com 2019-10-26T00:07:24+00:00 ffc379b42c85466e1dd4c8fee8268801f26d2ab8 - bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC 
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
Merge branch '2019-10-24-ti-imports' 2019-10-25T21:33:28+00:00 Tom Rini trini@konsulko.com 2019-10-25T21:33:28+00:00 15147dc6a96697880cf355ed9df127bd8c896f2c - Enable DFU on dra7xx boards - Further Keystone 3 platform improvements 
- Enable DFU on dra7xx boards
- Further Keystone 3 platform improvements
ram: k3-j721e: Add support for J721E DDR controller 2019-10-25T21:33:21+00:00 Kevin Scholz k-scholz@ti.com 2019-10-07T13:56:36+00:00 3bb3f266ee617384bb282a6818f675b5aca5c371 The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> 
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.

Signed-off-by: Kevin Scholz <k-scholz@ti.com
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ram: k3-am654: Do not rely on default values for certain DDR register 2019-10-25T21:33:21+00:00 James Doublesin doublesin@ti.com 2019-10-07T08:34:27+00:00 34f27b2e86b996483be30d05e3c753a4fc055adf Added the following registers to the DDR configuration: - ACIOCR0, - ACIOCR3, - V2H_CTL_REG, - DX8SLxDQSCTL. Modified enable_dqs_pd and disable_dqs_pd to only touch the associated bit fields for pullup and pulldown registers (to preserve slew rate and other bits in that same register). Also update the dts files in the same patch to maintain git bisectability. Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> 
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.

Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ram: k3-am654: add support for LPDDR4 and DDR3L DDRs 2019-10-25T21:33:21+00:00 James Doublesin doublesin@ti.com 2019-10-07T08:34:26+00:00 c78ac7a0c911da33683b8d88965a910b2dcbd144 Added training support for LPDDR4 and DDR3L DDRs. Also added/changed some register configuration to support all 3 DDR types Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> 
Added training support for LPDDR4 and DDR3L DDRs.  Also added/changed
some register configuration to support all 3 DDR types

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>