u-boot.git/drivers, branch v2020.10-rc3 Unnamed repository; edit this file 'description' to name the repository. Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell 2020-08-25T17:38:29+00:00 Tom Rini trini@konsulko.com 2020-08-25T14:24:40+00:00 9f9ecd3e4d7839e24c182fb7b24937e19b670f1b - Add basic Marvell/Cavium OcteonTX/TX2 support (Suneel) - Infrastructure changes to PCI uclass to support these SoC's (Suneel) - Add PCI, MMC & watchdog driver drivers for OcteonTX/TX2 (Suneel) - Increase CONFIG_SYS_MALLOC_F_LEN for qemu-x86 (Stefan) 
- Add basic Marvell/Cavium OcteonTX/TX2 support (Suneel)
- Infrastructure changes to PCI uclass to support these SoC's (Suneel)
- Add PCI, MMC & watchdog driver drivers for OcteonTX/TX2 (Suneel)
- Increase CONFIG_SYS_MALLOC_F_LEN for qemu-x86 (Stefan)
Merge tag 'i2c-bugfixes-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c 2020-08-25T12:19:41+00:00 Tom Rini trini@konsulko.com 2020-08-25T12:19:41+00:00 ec54217ddc6f52f3b7dad7a3fd6d8a3abd64ab7e i2c bugfixes for v2020.10 - fix some issues with octeon_i2c driver on ARM Octeon TX2 - fix link failure with CONFIG_SPL and CONFIG_I2C_MUX_PCA954x 
i2c bugfixes for v2020.10
- fix some issues with octeon_i2c driver on ARM Octeon TX2
- fix link failure with CONFIG_SPL and CONFIG_I2C_MUX_PCA954x
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv 2020-08-25T12:18:50+00:00 Tom Rini trini@konsulko.com 2020-08-25T12:18:50+00:00 078656186f1037894c45682ca74d0921de8a7010 - Sipeed Maix support S-mode. - Provide command sbi. - Use fdtdec_get_addr_size_auto_parent to get fu540 cache base address. - Fix a compiler error with CONFIG_SPL_SMP=n. - Fix sifive ram driver 32 compiler warnings. - Fix kendryte/pll.h redefine nop() warning. 
- Sipeed Maix support S-mode.
- Provide command sbi.
- Use fdtdec_get_addr_size_auto_parent to get fu540 cache base address.
- Fix a compiler error with CONFIG_SPL_SMP=n.
- Fix sifive ram driver 32 compiler warnings.
- Fix kendryte/pll.h redefine nop() warning.
watchdog: Add reset support for OcteonTX / TX2 2020-08-25T06:01:16+00:00 Suneel Garapati sgarapati@marvell.com 2019-10-21T23:09:36+00:00 af6ba90048afb4e0db3ff2480364286f230f8b91 Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2 platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> 
Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2
platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
mmc: Add MMC controller driver for OcteonTX / TX2 2020-08-25T06:01:16+00:00 Suneel Garapati sgarapati@marvell.com 2019-10-20T01:03:01+00:00 708598997db23d111b7693ed95454d990a82b3d5 Adds support for MMC controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Peng Fan <peng.fan@nxp.com> 
Adds support for MMC controllers found on OcteonTX or
OcteonTX2 SoC platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Peng Fan <peng.fan@nxp.com>
pci: Add PCI controller driver for OcteonTX / TX2 2020-08-25T06:01:16+00:00 Suneel Garapati sgarapati@marvell.com 2019-10-20T00:28:01+00:00 638d705a5400677280b8b82a894f9a0e8d685a8f Adds support for PCI ECAM/PEM controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> 
Adds support for PCI ECAM/PEM controllers found on OcteonTX
or OcteonTX2 SoC platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
ata: ahci: Add BAR index quirk for Cavium PCI SATA device 2020-08-25T06:01:16+00:00 Suneel Garapati sgarapati@marvell.com 2019-10-20T00:48:25+00:00 3f6f0cd8fd809287838153d355311f1499040758 For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0 instead of BAR5. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0
instead of BAR5.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
pci: pci-uclass: Check validity of ofnode 2020-08-25T06:01:16+00:00 Suneel Garapati sgarapati@marvell.com 2020-05-05T04:25:25+00:00 f0c369284d8da6691d3895d9d9d83015c141008a Add check if the referenced ofnode is valid. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> 
Add check if the referenced ofnode is valid.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
pci: pci-uclass: Add support for Alternate-RoutingID capability 2020-08-25T06:01:16+00:00 Suneel Garapati sgarapati@marvell.com 2019-10-24T01:40:36+00:00 a3fac3f395afc5ad7aeb01fb7ed2d87d07c87ab0 If ARI capability is found on device, use it to update next function number in bus scan and also helps to skip unnecessary bdf scans. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> 
If ARI capability is found on device, use it to update next function
number in bus scan and also helps to skip unnecessary bdf scans.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation 2020-08-25T06:01:16+00:00 Suneel Garapati sgarapati@marvell.com 2019-10-19T23:34:16+00:00 51eeae91c5e7b8f7c1bdf46aa6d6bb1675fd2ebc Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> 
Makes dm_pci_map_bar API available to map BAR for Virtual function
PCI devices which support Enhanced Allocation.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>