u-boot.git/drivers, branch v2021.01

cosmetic: fix typo in drivers/usb/Kconfig

2021-01-04T14:10:17+00:00

This commit fixes a simple typo: sPL --> SPL.

Signed-off-by: Marc Ferland

nvme: Use only 32-bit accesses in nvme_writeq/nvme_readq

2021-01-04T14:10:16+00:00

There might be hardware configurations where 64-bit data accesses
to NVMe registers are not supported properly.  This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit NVMe registers, similarly as it is done in Linux kernel.

This patch fixes operation of NVMe devices on RPi4 Broadcom BCM2711 SoC
based board, where the PCIe Root Complex, which is attached to the
system through the SCB bridge.

Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
the 64-bit wide register accesses initiated by the CPU are not properly
translated to a sequence of 32-bit PCIe accesses.
nvme_readq(), for example, always returns same value in upper and lower
32-bits, e.g. 0x3c033fff3c033fff which lead to NVMe devices to fail
probing.

This fix is analogous to commit 8e2ab05000ab ("usb: xhci: Use only
32-bit accesses in xhci_writeq/xhci_readq").

Cc: Sylwester Nawrocki 
Cc: Nicolas Saenz Julienne 
Cc: Matthias Brugger 
Reviewed-by: Stefan Roese 
Reviewed-by: Bin Meng 
Signed-off-by: Stefan Agner

Merge tag 'u-boot-imx-20201227' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

2020-12-28T12:44:03+00:00

Fixes for 2021.1
----------------

CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/5680

- fixes for Variscite dart6ul
- imx8mp : increase malloc area
- fixes for bx50v3
- imx8m: HS400ES and UHS for EVK
- imx8qm-rom7720: fix phy bind

Revert "arm64: a37xx: pci: Assert PERST# signal when unloading driver"

2020-12-28T08:42:06+00:00

This reverts commit 828d32621686aec593076d16445d39b9b8d49c05.

This change revers code which asserting PERST# signal when unloading
driver. Driver's remove callback is still there as it is used for other
functionality.

Asserting PERST# signal prior booting kernel is causing that A3720 boards
(Turris MOX and Espressobin) with stable Linux kernel versions 4.14 and
4.19 are not able to detect some PCIe cards (e.g. Compex WLE200 and WLE900)
and anymore. When PERST# signal is not asserted these cards are detected
correctly. As this is regression for existing stable Linux kernel versions
revert this problematic change in U-Boot.

To make cards working with OpenWRT 4.14 kernel it is needed to disable link
training prior booting kernel, which is already done in driver's remove
callback.

Described issue is in Linux kernel pci aardvark driver which is (hopefully)
fixed in latest upstream versions. Latest upstream versions should be able
to initialize PCIe bus and detects cards independently of the link training
and PERST# signal state.

So with this change, U-Boot on A3720 boards should be able to boot OpenWRT
4.14 kernel, stable 4.14 and 4.19 kernels and also latest mainline kernels.

Signed-off-by: Pali Rohár 
Reviewed-by: Stefan Roese

i2c: mxc_i2c: improve error message readability

2020-12-26T13:56:09+00:00

Use 0x%2lx to print the i2c bus base address in hexadecimal format
instead of printing as an integer.

Signed-off-by: Marc Ferland 
Reviewed-by: Fabio Estevam

Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi

2020-12-18T18:06:02+00:00

mtd: spi-nor-ids: add Micron MT25QL01G flash

2020-12-18T10:49:33+00:00

Add Micron MT25QL01G flash, used on AST2600 board.

Signed-off-by: Hongwei Zhang 
Reviewed-by: Jagan Teki

spi: ca_sflash: Add CAxxxx SPI Flash Controller

2020-12-18T10:46:37+00:00

Add SPI Flash controller driver for Cortina Access
CAxxxx SoCs

Signed-off-by: Pengpeng Chen 
Signed-off-by: Alex Nemirovsky 
CC: Vignesh R 
CC: Tom Rini 
[jagan: rebase on master]
Signed-off-by: Jagan Teki 
Reviewed-by: Jagan Teki

spi: dw: Add mem_ops

2020-12-18T10:46:37+00:00

The designware ssi device has "broken" chip select behaviour [1], and needs
specific manipulation to use the built-in chip select. The existing fix is
to use an external GPIO for chip select, but typically the K210 has SPI3
directly connected to a flash chip with dedicated pins. This makes it
impossible to use the spi_xfer function to use spi, since the CS is
de-asserted in between calls.  This patch adds an implementation of
exec_op, which gives correct behaviour when reading/writing spi flash.

This patch also rearranges the headers to conform to U-Boot style.

[1] https://lkml.org/lkml/2015/12/23/132

Signed-off-by: Sean Anderson 
Tested-by Eugeniy Paltsev 
Reviewed-by: Jagan Teki

spi: dw: Add support for multiple CTRLR0 layouts

2020-12-18T10:46:37+00:00

CTRLR0 can have several different layouts depending on the specific device
(dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis.
Update the driver to support three specific configurations: dw-apb-ssi with
SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi.

dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC
SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver
supported before this change. The register layout before version 3.23a is:

|   31 .. 16  |
| other stuff |

|   15 .. 10  | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 |
| other stuff |  TMOD  |  MODE  |  FRF   |  DFS   |

Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data
frames of 16 bits or less.

In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This
parameter defaults to 16 (resulting in the same layout as prior versions),
but may also be set to 32. To allow setting longer data frame sizes, a new
DFS_32 register was introduced:

|   31 .. 21  | 20 .. 16 |
| other stuff |  DFS_32  |

|   15 .. 10  | 9 .. 8 | 7 .. 6 | 5 .. 4 |  3 .. 0   |
| other stuff |  TMOD  |  MODE  |  FRF   | all zeros |

The old DFS field no longer controls the data frame size. To detect this
layout, we try writing 0xF to DFS. If we read back 0x0, then this device
has SSI_MAX_XFER_SIZE=32.

dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan
Kendryte K210 SoCs. The layout of ctrlr0 is:

|   31 .. 16  |
| other stuff |

|   15 .. 12  | 11 .. 10 | 9 .. 8 | 7 .. 6 | 4 .. 0 |
| other stuff |   TMOD   |  MODE  |  FRF   | DFS_32 |

The semantics of the fields have not changed since the previous version.
However, SSI_MAX_XFER_SIZE is effectively always 32.

To support these different layouts, we model our approach on the one
which the Linux kernel has taken. During probe, the driver calls an init
function stored in driver_data. This init function is responsible for
determining the layout of CTRLR0, and supplying the update_cr0 function.

The style of and information behind this commit is based on the Linux MMIO
driver for these devices. Specific reference was made to the series adding
support for Intel Keem Bay SoCs [1].

[1] https://lore.kernel.org/linux-spi/20200505130618.554-1-wan.ahmad.zainie.wan.mohamad@intel.com/

Signed-off-by: Sean Anderson 
Reviewed-by: Jagan Teki