u-boot.git/drivers, branch v2021.07-rc4

net: luton: remove address translation after ofnode_read_resource

2021-06-05T13:35:47Z

Removed call of ofnode_translate_address() after ofnode_read_resource in luton_switch.c:luton_probe(); it is unnecessary since the commit feb7ac457c20 ("dm: core: Add address translation in fdt_get_resource"). Fixes: feb7ac457c20 ("dm: core: Add address translation in fdt_get_resource") Reviewed-by: Ramon Fried Reported-by: Horatiu Vultur Signed-off-by: Patrick Delaunay

pwm: cros_ec: Rename "priv_auto_alloc_size" to "priv_auto"

2021-06-05T13:35:47Z

With commit 41575d8e4c33 ("dm: treewide: Rename auto_alloc_size members to be shorter") "priv_auto_alloc_size" was renamed to "priv_auto". This driver was sent to the mailing list before that change, merged after it, and still has the old form. Apply the rename here as well. Fixes: 1b9ee2882e6b ("pwm: Add a driver for Chrome OS EC PWM") Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass

of: addr: Remove call to dev_count_cells() in of_get_address()

2021-06-05T13:35:34Z

In of_get_address(), there is: dev_count_cells(dev, &na, &ns); followed by: bus->count_cells(dev, &na, &ns); but no codes in between use na/ns, hence the first call is useless. By dropping the first call, dev_count_cells() is now useless too. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

of: addr: Translate 'dma-ranges' for parent nodes missing 'dma-ranges'

2021-06-05T13:35:34Z

'dma-ranges' frequently exists without parent nodes having 'dma-ranges'. While this is an error for 'ranges', this is fine because DMA capable devices always have a translatable DMA address. Also, with no 'dma-ranges' at all, the assumption is that DMA addresses are 1:1 with no restrictions unless perhaps the device itself has implicit restrictions. This keeps in sync with Linux kernel commit: 81db12ee15cb: of/address: Translate 'dma-ranges' for parent nodes missing 'dma-ranges' Signed-off-by: Bin Meng Reviewed-by: Simon Glass

arm: a37xx: pci: Fix configuring PCIe resources

2021-06-04T09:32:41Z

The `ranges` DT property of the PCIe node is currently ignored by Aardvark driver - all entries are used as transparent PCIe MEM, despite some of them being defined for IO in DT. This is because the driver does not setup PCIe outbound windows and thus a default configuration is used. This can cause an external abort on CPU when a device driver tries to access non-MEM space. Setup the PCIe windows according to the `ranges` property for all non-MEM resources (currently only IO) and also non-transparent MEM resources. Because Linux expects that bootloader does not setup Aardvark PCIe windows, disable them before booting Linux. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese

arm: a37xx: pci: Fix DT compatible string to Linux' DT compatible

2021-06-04T09:32:41Z

Change DT compatible string for A3700 PCIe from 'marvell,armada-37xx-pcie' to 'marvell,armada-3700-pcie' to make U-Boot A3700 PCIe DT node compatible with Linux' DT node. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese

arm: a37xx: pci: Disable bus mastering when unloading driver

2021-06-04T09:32:41Z

Disable Root Bridge I/O space, memory space and bus mastering in Aardvark's remove method, which is called before booting Linux kernel. This ensures that PCIe device which was initialized and used by U-Boot cannot do new DMA transfers until Linux initializes PCI subsystem and loads appropriate drivers for the device. During initialization of PCI subsystem Linux in fact disables this bus mastering on Root Bridge (and later enables it when driver is loaded and configured), but there is a possibility of a small window after U-Boot boots Linux when bus mastering is enabled, which is not correct. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese

arm: a37xx: pci: Don't put link into LTSSM Recovery state during probe

2021-06-04T09:32:41Z

During our debugging of the Aardvark driver in Linux we have discovered that the PCIE_CORE_LINK_CTRL_STAT_REG register in fact controls standard PCIe Link Control Register for PCIe Root Bridge. This led us to discover that the name of the PCIE_CORE_LINK_TRAINING macro and the corresponding comment by this macro's usage is misleading; this bit in fact controls Retrain Link, which, according to PCIe base spec is defined as: A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. Entering Recovery state is normally done from LTSSM L0, L0s and L1 states. But since the pci-aardvark.c driver enables Link Training just a few lines above, the controller is not in L0 ready state yet. So setting aardvark bit PCIE_CORE_LINK_TRAINING does not actually enter Recovery state at this place. Moreover, trying to enter LTSSM Recovery state without other configuration is causing issues for some cards (e.g. Atheros AR9xxx and QCA9xxx). Since Recovery state is not entered, these issues are not triggered. Remove code which tries to enter LTSSM Recovery state completely. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese

drivers: pci: pcie_dw_common: fix Werror compilation error

2021-05-31T08:35:55Z

Fix compilation error when Werror is turned on. The warning could possible break some CI builds. Signed-off-by: Green Wan Reviewed-by: Leo Yu-Chi Liang

board: sifive: add HiFive Unmatched board support

2021-05-31T08:35:55Z

Add defconfig and board support for HiFive Unmatched. Signed-off-by: Green Wan Reviewed-by: Bin Meng Reviewed-by: Rick Chen