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<title>u-boot.git/drivers, branch v2022.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>usb: host: ehci-generic: Fix error check</title>
<updated>2022-07-04T12:00:36+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-07-02T00:45:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9125b4b021d81b72d946a08775d62355a59f6fab'/>
<id>9125b4b021d81b72d946a08775d62355a59f6fab</id>
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Commit 81755b8c20fe ("usb: host: ehci-generic: Make resets and clocks
optional") improved the error check to cover the reset property being
optional. However this was using the wrong error variable for the
check, so would now never fail.

Use the correct error variable for checking the result of
reset_get_bulk(), to actually report genuine errors.

Fixes: 81755b8c20fe ("usb: host: ehci-generic: Make resets and clocks optional")
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
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<pre>
Commit 81755b8c20fe ("usb: host: ehci-generic: Make resets and clocks
optional") improved the error check to cover the reset property being
optional. However this was using the wrong error variable for the
check, so would now never fail.

Use the correct error variable for checking the result of
reset_get_bulk(), to actually report genuine errors.

Fixes: 81755b8c20fe ("usb: host: ehci-generic: Make resets and clocks optional")
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>Merge commit 'ef5ba2cef4a08b68caaa9215fcac142d3025bbf7' of https://github.com/tienfong/uboot_mainline</title>
<updated>2022-07-01T13:14:32+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-07-01T13:14:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9fcc2fb3fec3f2f09594747e4c47f3758f79b9df'/>
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<pre>
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</entry>
<entry>
<title>drivers: clk: Update license for Intel N5X device</title>
<updated>2022-07-01T07:00:39+00:00</updated>
<author>
<name>Teik Heng Chong</name>
<email>teik.heng.chong@intel.com</email>
</author>
<published>2022-06-29T05:51:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ef5ba2cef4a08b68caaa9215fcac142d3025bbf7'/>
<id>ef5ba2cef4a08b68caaa9215fcac142d3025bbf7</id>
<content type='text'>
All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel,
update the license to use both GPL2.0 and BSD-3 Clause because this
copy of code may used for open source and internal project.

Signed-off-by: Teik Heng Chong &lt;teik.heng.chong@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
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<pre>
All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel,
update the license to use both GPL2.0 and BSD-3 Clause because this
copy of code may used for open source and internal project.

Signed-off-by: Teik Heng Chong &lt;teik.heng.chong@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>socfpga: arria10: Wait for fifo empty after writing bitstream</title>
<updated>2022-07-01T06:57:14+00:00</updated>
<author>
<name>Paweł Anikiel</name>
<email>pan@semihalf.com</email>
</author>
<published>2022-06-17T10:47:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5c53d9c0d955d046694e550e1c429fa509abb0c8'/>
<id>5c53d9c0d955d046694e550e1c429fa509abb0c8</id>
<content type='text'>
For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>socfpga: arria10: Improve bitstream loading speed</title>
<updated>2022-07-01T06:57:14+00:00</updated>
<author>
<name>Paweł Anikiel</name>
<email>pan@semihalf.com</email>
</author>
<published>2022-06-17T10:47:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8b1eee3730fc603fcacc5818b71a0e194bc55892'/>
<id>8b1eee3730fc603fcacc5818b71a0e194bc55892</id>
<content type='text'>
Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):

 * Change the size of the first fs read, so that all the subsequent
   reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
   This value was chosen so that in subsequent reads the fat fs driver
   doesn't have to allocate a temporary buffer in get_contents
   (assuming 8KiB clusters).

 * Change the buffer size to a larger value when reading to ddr
   (but not too large, because large transfers cause a stack overflow
   in the dwmmc driver).

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):

 * Change the size of the first fs read, so that all the subsequent
   reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
   This value was chosen so that in subsequent reads the fat fs driver
   doesn't have to allocate a temporary buffer in get_contents
   (assuming 8KiB clusters).

 * Change the buffer size to a larger value when reading to ddr
   (but not too large, because large transfers cause a stack overflow
   in the dwmmc driver).

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sysreset: socfpga: Use parent device for reading base address</title>
<updated>2022-07-01T06:57:14+00:00</updated>
<author>
<name>Paweł Anikiel</name>
<email>pan@semihalf.com</email>
</author>
<published>2022-06-17T10:47:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9ebca7095bdbb2843a37b1f36d7896a6cb21e4ab'/>
<id>9ebca7095bdbb2843a37b1f36d7896a6cb21e4ab</id>
<content type='text'>
This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>misc: atsha204a: Increase wake delay by tWHI</title>
<updated>2022-07-01T06:57:14+00:00</updated>
<author>
<name>Paweł Anikiel</name>
<email>pan@semihalf.com</email>
</author>
<published>2022-06-17T10:47:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=73d88cf9719e505eedb389d117704f806e4747d1'/>
<id>73d88cf9719e505eedb389d117704f806e4747d1</id>
<content type='text'>
From the ATSHA204A datasheet (document DS40002025A):

Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.

tWHI value can be found in table 7-2.

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
From the ATSHA204A datasheet (document DS40002025A):

Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.

tWHI value can be found in table 7-2.

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-rockchip-20220630' of https://source.denx.de/u-boot/custodians/u-boot-rockchip</title>
<updated>2022-07-01T02:36:41+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-07-01T02:36:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=33938636f0914983554238c983c7429f68224239'/>
<id>33938636f0914983554238c983c7429f68224239</id>
<content type='text'>
- Fix for rk3328 nonopi-r2s boot env;
- Fix for rk8xx pmic boot on power plug-in;
- Fix for tee.bin support in fit image;
- rk3288 board dts update or fix;
- Some rk3399 board fix;
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<pre>
- Fix for rk3328 nonopi-r2s boot env;
- Fix for rk8xx pmic boot on power plug-in;
- Fix for tee.bin support in fit image;
- rk3288 board dts update or fix;
- Some rk3399 board fix;
</pre>
</div>
</content>
</entry>
<entry>
<title>mtd: mxs_nand_spl: fix nand_command protocol violation</title>
<updated>2022-06-29T13:26:44+00:00</updated>
<author>
<name>Andrea Scian</name>
<email>andrea.scian@dave.eu</email>
</author>
<published>2022-06-21T20:05:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=05dcb5be507a0580a0fc57dd363c632ac4a6b3c4'/>
<id>05dcb5be507a0580a0fc57dd363c632ac4a6b3c4</id>
<content type='text'>
mxs_nand_command() implementation assume that it's working with a
LP NAND, which is a common case nowadays and thus uses two bytes
for column address.

However this is wrong for NAND_CMD_READID and NAND_CMD_PARAM, which
expects only one byte of column address, even for LP NANDs.
This leads to ONFI detection problem with some NAND manufacturer (like
Winbond) but not with others (like Samsung and Spansion)

We fix this with a simple workaround to avoid the 2nd byte column address
for those two commands.

Also align the code with nand_base to support 16 bit devices.

Tested on an iMX6SX device with:
* Winbond W29N04GVSIAA
* Spansion S34ML04G100TF100
* Samsung K9F4G08U00

Tested on imx8mn device with:
* Windbond W29N04GV

Signed-off-by: Andrea Scian &lt;andrea.scian@dave.eu&gt;
CC: Stefano Babic &lt;sbabic@denx.de&gt;
Signed-off-by: Michael Trimarchi &lt;michael@amarulasolutions.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@denx.de&gt;
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<pre>
mxs_nand_command() implementation assume that it's working with a
LP NAND, which is a common case nowadays and thus uses two bytes
for column address.

However this is wrong for NAND_CMD_READID and NAND_CMD_PARAM, which
expects only one byte of column address, even for LP NANDs.
This leads to ONFI detection problem with some NAND manufacturer (like
Winbond) but not with others (like Samsung and Spansion)

We fix this with a simple workaround to avoid the 2nd byte column address
for those two commands.

Also align the code with nand_base to support 16 bit devices.

Tested on an iMX6SX device with:
* Winbond W29N04GVSIAA
* Spansion S34ML04G100TF100
* Samsung K9F4G08U00

Tested on imx8mn device with:
* Windbond W29N04GV

Signed-off-by: Andrea Scian &lt;andrea.scian@dave.eu&gt;
CC: Stefano Babic &lt;sbabic@denx.de&gt;
Signed-off-by: Michael Trimarchi &lt;michael@amarulasolutions.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: Add option to prevent booting on power plug-in</title>
<updated>2022-06-29T03:42:10+00:00</updated>
<author>
<name>Chris Morgan</name>
<email>macromorgan@hotmail.com</email>
</author>
<published>2022-05-27T18:18:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=30975fb73d51f65d95e9508e4af9c85badd5388c'/>
<id>30975fb73d51f65d95e9508e4af9c85badd5388c</id>
<content type='text'>
For Rockchip boards with the all rk8xx series PMICs (excluding the
rk808), it is sometimes desirable to not boot whenever the device is
plugged in. An example would be for the Odroid Go Advance.

This provides a configurable option to check the PMIC says it was
powered because of a plug-in event. If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.

This patch parallels the work done in the following patch series:
https://lore.kernel.org/u-boot/20220121133732.2397273-1-andre.przywara@arm.com/

Signed-off-by: Chris Morgan &lt;macromorgan@hotmail.com&gt;
Reviewed-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
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<pre>
For Rockchip boards with the all rk8xx series PMICs (excluding the
rk808), it is sometimes desirable to not boot whenever the device is
plugged in. An example would be for the Odroid Go Advance.

This provides a configurable option to check the PMIC says it was
powered because of a plug-in event. If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.

This patch parallels the work done in the following patch series:
https://lore.kernel.org/u-boot/20220121133732.2397273-1-andre.przywara@arm.com/

Signed-off-by: Chris Morgan &lt;macromorgan@hotmail.com&gt;
Reviewed-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
</pre>
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</content>
</entry>
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