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<title>u-boot.git/drivers, branch v2022.07-rc4</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers?h=v2022.07-rc4</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers?h=v2022.07-rc4'/>
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<updated>2022-06-03T15:15:24Z</updated>
<entry>
<title>net: enetc: unregister mdiobus</title>
<updated>2022-06-03T15:15:24Z</updated>
<author>
<name>Michael Walle</name>
<email>michael@walle.cc</email>
</author>
<published>2022-05-31T16:36:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7704b7fd673a603805f5ddd8807f69d4bc3b9188'/>
<id>urn:sha1:7704b7fd673a603805f5ddd8807f69d4bc3b9188</id>
<content type='text'>
If the device fails to probe - for example, when there is no
ethaddr set - then the private data is automatically freed
but the mdiobus remains registered.

Fixes: 1e354cb39314 ("drivers: net: fsl_enetc: register internal MDIO bus")
Signed-off-by: Michael Walle &lt;michael@walle.cc&gt;
</content>
</entry>
<entry>
<title>net: e1000: Depend on CONFIG_PCI</title>
<updated>2022-05-26T14:32:27Z</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@seco.com</email>
</author>
<published>2022-04-26T18:35:33Z</published>
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<id>urn:sha1:d64ac8549d97cfc37bd629a60f0d502bcd3ee9c7</id>
<content type='text'>
This driver depends on PCI. Update the Kconfig accordingly.

Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
Reviewed-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Ramon Fried &lt;rfried.dev@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'xilinx-for-v2022.07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblaze</title>
<updated>2022-05-25T13:50:08Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-05-25T13:50:08Z</published>
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<id>urn:sha1:661f5400754750df4104b6466942c8b62897340d</id>
<content type='text'>
Xilinx changes for v2022.07-rc4

zynqmp:
- Fix DP PLL configuration for zcu102/zcu106 and SOM
- Fix split mode for starting R5s
- DT fixes
- Remove firmware node for mini configurations
- Wire TEE for multi DTB fit image

xilinx:
- Handle board_get_usable_ram_top(0) properly

phy:
- Extend psgtr timeout

mmc:
- Fix mini configuration which misses zynqmp_pm_is_function_supported()
</content>
</entry>
<entry>
<title>Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi</title>
<updated>2022-05-25T03:29:00Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-05-25T03:29:00Z</published>
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<id>urn:sha1:7e0edcadb09d55d5319fdc862041fd1b874476f5</id>
<content type='text'>
The bulk of it is (finally!) some DT sync from the kernel. We refrained
from syncing one incompatible change, as this would spoil booting Linux
kernels before v5.13 with U-Boot's DT (via UEFI, for instance).
I test booted Linux v5.18 and v5.4 with that new DT on some boards, and
the headless peripherals (MMC, USB, Ethernet) seemed to work.
The rest are fixes:
- silencing missing clock warnings due to the new pinctrl driver
- fixing "UART0 on PortF", allowing UART access through the SD card pins
- add an F1C100s clock driver, to enable MMC support (SPI comes later)
- some cleanups for CONS_INDEX_n in Kconfig

Tested on BananaPi-M1, Pine64-LTS, Pine-H64, X96-Mate (H616) and
OrangePi-Zero.
</content>
</entry>
<entry>
<title>Merge tag 'tpm-24052022' of https://source.denx.de/u-boot/custodians/u-boot-tpm</title>
<updated>2022-05-24T13:03:34Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-05-24T13:03:34Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1b04a961c6bcb9768f517198890cac680ee532e8'/>
<id>urn:sha1:1b04a961c6bcb9768f517198890cac680ee532e8</id>
<content type='text'>
Add support for i2c devices
</content>
</entry>
<entry>
<title>serial: Remove obsolete CONS_INDEX_n Kconfig options</title>
<updated>2022-05-24T00:46:06Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-05-09T05:10:55Z</published>
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<id>urn:sha1:7495051219b64ec0e8fac8930586dc10666530da</id>
<content type='text'>
These were only ever implied by sunxi platforms, and that usage has
been removed. Current practice is to specify CONFIG_CONS_INDEX in each
board's defconfig.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: add and use dummy gate clocks</title>
<updated>2022-05-24T00:16:15Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-05-05T00:25:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d6cb09d89d52d087881695c1f4e5e1ff26328267'/>
<id>urn:sha1:d6cb09d89d52d087881695c1f4e5e1ff26328267</id>
<content type='text'>
Some devices enumerate various clocks in their DT, and many drivers
just blanketly try to enable all of them. This creates problems
since we only model a few gate clocks, and the clock driver outputs
a warning when a clock is not described:
=========
sunxi_set_gate: (CLK#3) unhandled
=========

Some clocks don't have an enable bit, or are already enabled in a
different way, so we might want to just ignore them.

Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
a GATE_DUMMY macro that can be used in the clock description array.
Define a few clocks, used by some pinctrl devices, that way to suppress
the runtime warnings.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: add PIO bus gate clocks</title>
<updated>2022-05-24T00:15:09Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-05-04T21:10:28Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=444ab3569bae32daed9c05fb10f87d907cc180ff'/>
<id>urn:sha1:444ab3569bae32daed9c05fb10f87d907cc180ff</id>
<content type='text'>
The introduction of the DM pinctrl driver made its probe function enable
all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and
variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device.
So far we didn't describe those clocks in our clock driver.
As we enable them already in the SPL, the devices happen to work, but
the clock driver still complains about not finding those clocks:
=========
sunxi_set_gate: (CLK#58) unhandled
=========

Add the one-liners that are needed to announce the gate bit for those
clocks, to silence that message on the console.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: h6_r: Correct the driver name</title>
<updated>2022-05-24T00:15:01Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-04-23T21:07:16Z</published>
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<id>urn:sha1:596247e54b6243c53921a936fe3ce5ef031a702d</id>
<content type='text'>
H6 is from the sun50i family, not sun6i.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>mmc: sunxi: Remove unnecessary pinmux option dependency</title>
<updated>2022-05-24T00:14:51Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-04-10T05:13:34Z</published>
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<id>urn:sha1:818e1636ac5c4c4d67576dccca2d16e87cf176f2</id>
<content type='text'>
Now that the pinmux conflict is handled in the board code (by skipping
setup for the one conflicting MMC controller), the driver does not need
to be entirely disabled based on the UART pinmux.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
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