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<title>u-boot.git/drivers, branch v2022.07-rc5</title>
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<entry>
<title>Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of https://github.com/tienfong/uboot_mainline</title>
<updated>2022-06-17T13:35:28+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-06-17T13:35:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f0843e0c0ab2c05da81b89b2c0ce7955510aff8a'/>
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<pre>
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<entry>
<title>ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched</title>
<updated>2022-06-17T08:27:05+00:00</updated>
<author>
<name>Dinesh Maniyam</name>
<email>dinesh.maniyam@intel.com</email>
</author>
<published>2022-06-01T10:49:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=32e0379143b433e29d76404f5f4c279067e48853'/>
<id>32e0379143b433e29d76404f5f4c279067e48853</id>
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Convert the constant integer to 'phys_size_t' to avoid overflow
when calculating the SDRAM size.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
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Convert the constant integer to 'phys_size_t' to avoid overflow
when calculating the SDRAM size.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
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<entry>
<title>drivers: cache: ncore: Disable snoop filter</title>
<updated>2022-06-17T08:27:05+00:00</updated>
<author>
<name>Dinesh Maniyam</name>
<email>dinesh.maniyam@intel.com</email>
</author>
<published>2022-06-01T07:57:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d192adafebcd5e742a229aedbdcc7d6957d68f02'/>
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There is hardware bug in NCORE CCU IP and it is causing an issue in the
coherent directory tracking of outstanding cache lines.
The workaround is disabling snoop filter.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
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<pre>
There is hardware bug in NCORE CCU IP and it is causing an issue in the
coherent directory tracking of outstanding cache lines.
The workaround is disabling snoop filter.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</pre>
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<entry>
<title>usb: host: ehci-generic: Make resets and clocks optional</title>
<updated>2022-06-16T19:22:55+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-06-07T23:42:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=81755b8c20fe8ab7e10bd3a15fd48d37426ee45d'/>
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The generic EHCI binding does not *require* resets and clocks
properties, and indeed for instance the Allwinner A20 SoCs does not
need or define any resets in its DT.

Don't easily give up if clk_get_bulk() or reset_get_bulk() return an
error, but check if that is due to the DT simply having no entries for
either of them.

This fixes USB operation on all boards with an Allwinner A10 or A20 SoC,
which were reporting an error after commit ba96176ab70e2999:
=======================
Bus usb@1c14000: ehci_generic usb@1c14000: Failed to get resets (err=-2)
probe failed, error -2
=======================

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
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<pre>
The generic EHCI binding does not *require* resets and clocks
properties, and indeed for instance the Allwinner A20 SoCs does not
need or define any resets in its DT.

Don't easily give up if clk_get_bulk() or reset_get_bulk() return an
error, but check if that is due to the DT simply having no entries for
either of them.

This fixes USB operation on all boards with an Allwinner A10 or A20 SoC,
which were reporting an error after commit ba96176ab70e2999:
=======================
Bus usb@1c14000: ehci_generic usb@1c14000: Failed to get resets (err=-2)
probe failed, error -2
=======================

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</pre>
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</entry>
<entry>
<title>crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()</title>
<updated>2022-06-16T19:22:54+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2022-04-29T13:34:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=41b2182af73efcdfd074570976264dddacee5b70'/>
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While working on an LX2160 based board and updating to latest mainline
I noticed problems using the HW accelerated hash functions on this
platform, when trying to boot a FIT Kernel image. Here the resulting
error message:

   Using 'conf-freescale_lx2160a.dtb' configuration
   Trying 'kernel-1' kernel subimage
   Verifying Hash Integrity ... sha256Error: Address arguments are not aligned
CAAM was not setup properly or it is faulty
 error!
Bad hash value for 'hash-1' hash node in 'kernel-1' image node
Bad Data Hash
ERROR: can't get kernel image!

Testing and checking with Gaurav Jain from NXP has revealed, that this
alignment check is not necessary here at all. So let's remove this
check completely.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Gaurav Jain &lt;gaurav.jain@nxp.com&gt;
Cc: dullfire@yahoo.com
Reviewed-by: Gaurav Jain &lt;gaurav.jain@nxp.com&gt;
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<pre>
While working on an LX2160 based board and updating to latest mainline
I noticed problems using the HW accelerated hash functions on this
platform, when trying to boot a FIT Kernel image. Here the resulting
error message:

   Using 'conf-freescale_lx2160a.dtb' configuration
   Trying 'kernel-1' kernel subimage
   Verifying Hash Integrity ... sha256Error: Address arguments are not aligned
CAAM was not setup properly or it is faulty
 error!
Bad hash value for 'hash-1' hash node in 'kernel-1' image node
Bad Data Hash
ERROR: can't get kernel image!

Testing and checking with Gaurav Jain from NXP has revealed, that this
alignment check is not necessary here at all. So let's remove this
check completely.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Gaurav Jain &lt;gaurav.jain@nxp.com&gt;
Cc: dullfire@yahoo.com
Reviewed-by: Gaurav Jain &lt;gaurav.jain@nxp.com&gt;
</pre>
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</entry>
<entry>
<title>Merge tag 'u-boot-imx-20220616' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx</title>
<updated>2022-06-16T12:38:46+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-06-16T12:38:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9abfbef57f55f31e42940ac2a18ebccfb087e5c6'/>
<id>9abfbef57f55f31e42940ac2a18ebccfb087e5c6</id>
<content type='text'>
u-boot-imx-20220616
-------------------

Fixes for 2022.07 + Toradex apalis-imx8 (missed in last PR)

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12322
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u-boot-imx-20220616
-------------------

Fixes for 2022.07 + Toradex apalis-imx8 (missed in last PR)

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12322
</pre>
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</entry>
<entry>
<title>ddr: altera: Stratix10: Use phys_size_t for memory size</title>
<updated>2022-06-16T08:10:58+00:00</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2022-04-27T04:52:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=39bbcc341bda435899cb623a19d20727ca98c67a'/>
<id>39bbcc341bda435899cb623a19d20727ca98c67a</id>
<content type='text'>
Replace with phys_size_t for all memory size variables declaration
for the sake of scalability. phys_size_t is defined in
/arch/arm/include/asm/types.h.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
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<pre>
Replace with phys_size_t for all memory size variables declaration
for the sake of scalability. phys_size_t is defined in
/arch/arm/include/asm/types.h.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ddr: altera: Ignore bit[7-4] for both seq2core &amp; core2seq handshake in HPS</title>
<updated>2022-06-16T08:10:44+00:00</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2022-04-27T04:27:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ee06c5390f2f1e2f1bc23e14a7cd8665c1e42ff4'/>
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<content type='text'>
Bit[7-4] for both register seq2core and core2seq handshake in HPS are not
required for triggering DDR re-calibration or resetting EMIF. So, ignoring
these bits just for playing it safe.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
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<pre>
Bit[7-4] for both register seq2core and core2seq handshake in HPS are not
required for triggering DDR re-calibration or resetting EMIF. So, ignoring
these bits just for playing it safe.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-pmic</title>
<updated>2022-06-16T03:11:30+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-06-16T03:11:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fd27812e520881d73bd97a2c034f3b5ecc361c4b'/>
<id>fd27812e520881d73bd97a2c034f3b5ecc361c4b</id>
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</pre>
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</entry>
<entry>
<title>intel: n5x: ddr: update license</title>
<updated>2022-06-15T09:48:22+00:00</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2022-06-10T11:18:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=166e5b82a3f49239f67ac5f0d6df8abeb6ca0bdd'/>
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<content type='text'>
All the source code of sdram_n5x.c are from Intel, update the license to
use both GPL2.0 and BSD-3 Clause because this copy of code may used for
open source and internal project.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
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<pre>
All the source code of sdram_n5x.c are from Intel, update the license to
use both GPL2.0 and BSD-3 Clause because this copy of code may used for
open source and internal project.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</pre>
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