u-boot.git/drivers, branch v2023.01-rc1Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/drivers?h=v2023.01-rc12022-11-07T06:46:28Zpinctrl: mvebu: Add AlleyCat5 support2022-11-07T06:46:28ZChris Packhamjudge.packham@gmail.com2022-11-05T04:23:58Zurn:sha1:c2499382146664e19b95292888158d9c844f4032
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
usb: ehci: ehci-marvell: Support for marvell,ac5-ehci2022-11-07T06:46:28ZChris Packhamjudge.packham@gmail.com2022-11-05T04:23:57Zurn:sha1:515fe1ee4ecca7162a30a9b495582cc6d18c3593
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
net: mvneta: Add support for AlleyCat52022-11-07T06:46:28ZChris Packhamjudge.packham@gmail.com2022-11-05T04:23:56Zurn:sha1:aaee5720f25e24d2f8d4164efb7ef7afcc2a534d
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
usb: ohci: Use a flexible array member for portstatus2022-11-03T22:24:09ZSamuel Hollandsamuel@sholland.org2022-10-31T04:15:12Zurn:sha1:f4917b4933458a5e5c6da7e6e2e74137e62cf596
The struct is only used to overlay the MMIO region, so the behavior is
the same. This obsoletes the Kconfig option for the number of ports.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Merge branch '2022-11-02-assorted-updates'2022-11-03T12:29:10ZTom Rinitrini@konsulko.com2022-11-03T12:29:10Zurn:sha1:36bc9b6113ca96ca5c0d821195adede38395befd
- Improve arm semihosting, NPCM8xx pinctrl driver, SP804 uclass timer
driver (and enable on relevant platforms), pvblock cleanup, eeprom cmd
bugfix, add RTI watchdog nodes to k3-am64-main, evb-ast2500 config
updates.
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv2022-11-03T12:27:44ZTom Rinitrini@konsulko.com2022-11-03T12:27:44Zurn:sha1:c07babda65a47439b4f02bbb3204dfcb8679edc1spi: Add Microchip PolarFire SoC QSPI driver2022-11-03T05:27:56ZPadmarao Begaripadmarao.begari@microchip.com2022-10-27T06:02:01Zurn:sha1:eac3bbe5d84cd71201045b8c5cdafa0f3cc4ebda
Add QSPI driver code for the Microchip PolarFire SoC.
This driver supports the QSPI standard, dual and quad
mode interfaces.
Co-developed-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
riscv: Rename Andes PLIC to PLICSW2022-11-03T05:27:56ZYu Chien Peter Linpeterlin@andestech.com2022-10-25T15:03:50Zurn:sha1:a5dfa3b8a0f7ad555495bad1386613d2de4ba619
As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
led: led_pwm: typo 'iverted' on code comment2022-11-02T17:58:17ZNylon Chennylon.chen@sifive.com2022-10-27T06:25:37Zurn:sha1:3708739ef217bb1fed2ead5062875e97c81fc822
change iverted to inverted.
Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
treewide: Remove the unnecessary space before semicolon2022-11-02T17:58:17ZBin Mengbmeng@tinylab.org2022-10-26T04:40:07Zurn:sha1:ea253ad7b53f4ec3b614cebcc29d5905f10a23e3
%s/return ;/return;
Signed-off-by: Bin Meng <bmeng@tinylab.org>