u-boot.git/drivers, branch v2023.01-rc2

usb: gadget: dfu: Fix the unchecked length field

2022-11-21T14:23:00+00:00

DFU implementation does not bound the length field in USB
DFU download setup packets, and it does not verify that
the transfer direction. Fixing the length and transfer
direction.

CVE-2022-2347

Signed-off-by: Venkatesh Yadav Abbarapu 
Reviewed-by: Marek Vasut

clk: microchip: mpfs: fix criticality of peripheral clocks

2022-11-15T07:37:17+00:00

Sync the critical clocks in the U-Boot driver with those marked as
critical in Linux. The Linux driver has an explanation of why each clock
is considered to be critical, so import that too.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari

clk: microchip: mpfs: fix periph clk parentage

2022-11-15T07:37:17+00:00

Not all "periph" clocks are children of the AHB clock, some have the AXI
clock as their parent & the mtimer clock is derived from the external
reference clock directly. Stop assuming the AHB clock to be the parent
of all "periph" clocks and define their correct parents instead.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari 
Tested-by: Padmarao Begari

clk: microchip: mpfs: fix reference clock handling

2022-11-15T07:37:17+00:00

The original devicetrees for PolarFire SoC messed up & defined the
msspll's output as a fixed-frequency, 600 MHz clock & used that as the
input for the clock controller node. The msspll is not a fixed
frequency clock and later devicetrees handled this properly. Check the
devicetree & if it is one of the fixed ones, register the msspll.
Otherwise, skip registering it & pass the reference clock directly to
the cfg clock registration function so that existing devicetrees are
not broken by this change.

As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for
it, based on the one in Linux.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari 
Tested-by: Padmarao Begari

clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()

2022-11-15T07:37:17+00:00

Currently the clock driver for PolarFire SoC takes a very naive approach
to the relationship between clocks. It reads the dt to get an input
clock, assumes that that is fixed frequency, reads the "clock-frequency"
property & uses that to set up both the "cfg" and "periph" clocks.

Simplifying for the sake of incremental fixes, the "correct" parentage for
the clocks currently supported in U-Boot is that the "cfg" clocks should
be children of the fixed frequency clock in the dt. The AHB clock is one
of these "cfg" clocks and is the parent of the "periph" clocks.

Instead of passing the clock rate of the fixed-frequency clock to the
"cfg" and "periph" registration functions and the name of the parents,
pass their actual parents & use clk_get_rate() to determine their parents
rates.

The "periph" clocks are purely gate clocks and should not be reading the
AHB clocks registers to determine their rates, as they can simply report
the output of clk_get_rate() on their parent.

Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari

Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

2022-11-14T14:33:36+00:00

For 2022.01
-----------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083

- Fix UART
- moved to binman (MX8 boards)
- Toradex: sync DTS with Linux
- Gateworks: fixes
- New boards : MSC SM2S iMX8MP

i2c: i2c-gpio: add newline

2022-11-14T06:24:47+00:00

Add newline at the end of the printed string.

Signed-off-by: Sergei Antonov 
Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher

i2c: microchip: fix erroneous late ack send

2022-11-14T06:21:58+00:00

A late ack is currently being sent at the end of a transfer due to
incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
bit is being written to the controller's control reg after the last
byte has been received, causing it to sent another byte with the ack.
Instead, the AA flag should be written to the control register when
the penultimate byte is read so it is sent out for the last byte.

Reported-by: Andreas Buerkler 
Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver")
Signed-off-by: Conor Dooley 
Reviewed-by: Padmarao Begari 
Reviewed-by: Heiko Schocher 

Removed Tag by hs: Fixes: 0190d48488 ("i2c: microchip: fix ack sending logic")

i2c: microchip: fix ack sending logic

2022-11-14T06:20:10+00:00

"Master receive mode" was not correctly sending ACKs/NACKs in the
interrupt handler. Bring the handling of M_SLAR_ACK, M_RX_DATA_ACKED &
M_RX_DATA_NACKED in line with the Linux driver.

Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver")
Reported-by: Shravan Chippa 
Signed-off-by: Conor Dooley 
Reviewed-by: Padmarao Begari 
Reviewed-by: Heiko Schocher

Revert "serial: mxc: have putc use the TXFIFO"

2022-11-12T13:16:26+00:00

This reverts commit c7878a0483c59c48a730123bc0f4659fd40921bf.

Since commit c7878a0483c5 ("serial: mxc: have putc use the TXFIFO"),
serial console corruption can be seen when priting inside board_init().

Revert it to avoid the regression.

Reported-by: Tim Harvey 
Signed-off-by: Fabio Estevam 
Acked-by: Tim Harvey