<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers, branch v2023.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>rockchip: Fix incorrect constant name in RAM init code</title>
<updated>2023-04-02T16:57:12+00:00</updated>
<author>
<name>David Sebek</name>
<email>dasebek@gmail.com</email>
</author>
<published>2023-03-30T21:51:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=86169cdcb0ec53c93e27f7a6c983c33862a1f616'/>
<id>86169cdcb0ec53c93e27f7a6c983c33862a1f616</id>
<content type='text'>
A condition in the rk3399 RAM initialization code used the old
CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the
condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A condition in the rk3399 RAM initialization code used the old
CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the
condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>scsi: typo supporedt</title>
<updated>2023-04-01T08:11:50+00:00</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2023-03-26T15:08:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=854aaf9024fc70cae31672eb3db1583d8f88e94d'/>
<id>854aaf9024fc70cae31672eb3db1583d8f88e94d</id>
<content type='text'>
%s/supporedt/supported/

Fixes: edca8cf72130 ("Convert CONFIG_SCSI_AHCI_PLAT et al to Kconfig")
Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
%s/supporedt/supported/

Fixes: edca8cf72130 ("Convert CONFIG_SCSI_AHCI_PLAT et al to Kconfig")
Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sysreset: gpio: fix gpio_reboot_request return value</title>
<updated>2023-03-30T19:32:52+00:00</updated>
<author>
<name>Jonathan Liu</name>
<email>net147@gmail.com</email>
</author>
<published>2023-03-28T06:44:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a47164dfc1ef899ef9ddc6d8f2a17f0e9e90ef34'/>
<id>a47164dfc1ef899ef9ddc6d8f2a17f0e9e90ef34</id>
<content type='text'>
It should return -EINPROGRESS if successful otherwise sysreset-uclass
will continue to the next sysreset device.

Signed-off-by: Jonathan Liu &lt;net147@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
It should return -EINPROGRESS if successful otherwise sysreset-uclass
will continue to the next sysreset device.

Signed-off-by: Jonathan Liu &lt;net147@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'rpi-2023.04' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi</title>
<updated>2023-03-24T21:00:41+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-03-24T21:00:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=78f67f11a9920ef988cbff5341616695c3e87ebd'/>
<id>78f67f11a9920ef988cbff5341616695c3e87ebd</id>
<content type='text'>
- Fixes for booting newer revs of the SoC in the Raspberry Pi 4
- Propagate some firmware DT properties to the loaded DT
- Update the Zero2W upstream DT name
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
- Fixes for booting newer revs of the SoC in the Raspberry Pi 4
- Propagate some firmware DT properties to the loaded DT
- Update the Zero2W upstream DT name
</pre>
</div>
</content>
</entry>
<entry>
<title>mmc: bcm2835-host: let firmware manage the clock divisor</title>
<updated>2023-03-24T14:43:20+00:00</updated>
<author>
<name>Vincent Fazio</name>
<email>vfazio@xes-inc.com</email>
</author>
<published>2021-09-14T18:19:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=85bdd28d2bb0827f311913e00e4e338f8e4e6565'/>
<id>85bdd28d2bb0827f311913e00e4e338f8e4e6565</id>
<content type='text'>
Newer firmware can manage the SDCDIV clock divisor register, allowing
the divisor to scale with the core as necessary.

Leverage this ability if the firmware supports it.

Adapted from the following raspberrypi Linux kernel commit:

  bcm2835-sdhost: Firmware manages the clock divisor
  https://github.com/raspberrypi/linux/commit/08532d242d7702ae0add95096aa49c5e96e066e2

Signed-off-by: Vincent Fazio &lt;vfazio@xes-inc.com&gt;
Signed-off-by: Peter Robinson &lt;pbrobinson@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Newer firmware can manage the SDCDIV clock divisor register, allowing
the divisor to scale with the core as necessary.

Leverage this ability if the firmware supports it.

Adapted from the following raspberrypi Linux kernel commit:

  bcm2835-sdhost: Firmware manages the clock divisor
  https://github.com/raspberrypi/linux/commit/08532d242d7702ae0add95096aa49c5e96e066e2

Signed-off-by: Vincent Fazio &lt;vfazio@xes-inc.com&gt;
Signed-off-by: Peter Robinson &lt;pbrobinson@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dma: ti: k3-udma: Fix channel hang on teardown</title>
<updated>2023-03-22T16:51:15+00:00</updated>
<author>
<name>Vignesh Raghavendra</name>
<email>vigneshr@ti.com</email>
</author>
<published>2023-03-08T04:12:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f8461352b84ea66ad03d3231a5056643ab73515d'/>
<id>f8461352b84ea66ad03d3231a5056643ab73515d</id>
<content type='text'>
Setting RX flow error handling will stall the channel until descriptors
are available to move RX data. Setting this bit causes issues when
tearing down ethernet DMA channel at the end of TFTP transfer as
unrelated network packets can cause teardown to stall indefinitely waiting
for driver to queue add more desc leading to channel hang with error
logs:
udma_stop_dev2mem TIMEOUT !
udma_stop_dev2mem: peer not stopped TIMEOUT !
udma_stop_dev2mem TIMEOUT !

Fix this by clearing rx_error_handling similar to how its done for UDMA
as part of udma_alloc_rchan_sci_req()

This fixes occasional TFTP Failures seen when downloading multiple files
one after the other on AM64/AM62 SoCs.

Fixes: 9a92851c33e8 ("dma: ti: k3-udma: Add BCDMA and PKTDMA support")
Reported-by: Nishanth Menon &lt;nm@ti.com&gt;
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Setting RX flow error handling will stall the channel until descriptors
are available to move RX data. Setting this bit causes issues when
tearing down ethernet DMA channel at the end of TFTP transfer as
unrelated network packets can cause teardown to stall indefinitely waiting
for driver to queue add more desc leading to channel hang with error
logs:
udma_stop_dev2mem TIMEOUT !
udma_stop_dev2mem: peer not stopped TIMEOUT !
udma_stop_dev2mem TIMEOUT !

Fix this by clearing rx_error_handling similar to how its done for UDMA
as part of udma_alloc_rchan_sci_req()

This fixes occasional TFTP Failures seen when downloading multiple files
one after the other on AM64/AM62 SoCs.

Fixes: 9a92851c33e8 ("dma: ti: k3-udma: Add BCDMA and PKTDMA support")
Reported-by: Nishanth Menon &lt;nm@ti.com&gt;
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh</title>
<updated>2023-03-21T15:52:55+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-03-21T15:52:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e37be8484f025137d5073406641b1c731c19b3e1'/>
<id>e37be8484f025137d5073406641b1c731c19b3e1</id>
<content type='text'>
A single reset controller driver (part of the clock driver) fix
for v2023.04 release.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A single reset controller driver (part of the clock driver) fix
for v2023.04 release.
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: renesas: Pack reset identifier before look up</title>
<updated>2023-03-20T01:46:44+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2023-03-18T11:30:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=afafaa2a8f3f0ef38fc55c5d830890adb508549f'/>
<id>afafaa2a8f3f0ef38fc55c5d830890adb508549f</id>
<content type='text'>
The reset identifier must be processed via MOD_CLK_PACK() before it is
used to look up register and bit within reset_regs or reset_clear_regs
arrays, otherwise completely bogus register and bit is picked from the
arrays, one which may even be out of range.

Fixes: 326e05c5e21 ("clk: renesas: Add and enable CPG reset driver")
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The reset identifier must be processed via MOD_CLK_PACK() before it is
used to look up register and bit within reset_regs or reset_clear_regs
arrays, otherwise completely bogus register and bit is picked from the
arrays, one which may even be out of range.

Fixes: 326e05c5e21 ("clk: renesas: Add and enable CPG reset driver")
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: timer: rockchip_timer: fix compatible and driver name</title>
<updated>2023-03-19T06:12:01+00:00</updated>
<author>
<name>Johan Jonker</name>
<email>jbx6244@gmail.com</email>
</author>
<published>2023-03-07T15:30:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=791c7ac79274e2c3aa316da90fb3cc2411d5c5e8'/>
<id>791c7ac79274e2c3aa316da90fb3cc2411d5c5e8</id>
<content type='text'>
In the binding for the Rockchip timer the compatible string
consists of a SoC orientated string and a fall back string
"rockchip,rk3288-timer", so remove all unneeded ones and
fix driver name.

Signed-off-by: Johan Jonker &lt;jbx6244@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In the binding for the Rockchip timer the compatible string
consists of a SoC orientated string and a fall back string
"rockchip,rk3288-timer", so remove all unneeded ones and
fix driver name.

Signed-off-by: Johan Jonker &lt;jbx6244@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: sdhci: rk3568: bypass DLL when clk &lt;= 52 MHz</title>
<updated>2023-03-19T06:12:00+00:00</updated>
<author>
<name>Vasily Khoruzhick</name>
<email>anarsoul@gmail.com</email>
</author>
<published>2023-03-09T01:28:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2321a991bbb5f0de0781df09d332ee068426e264'/>
<id>2321a991bbb5f0de0781df09d332ee068426e264</id>
<content type='text'>
For Rockchip platform, DLL bypass bit and start bit need to be set if
DLL is not locked.

With this change applied eMMC in my NanoPi R5S can run at 52 MHz.

Based on linux commit b75a52b0dda3 ("mmc: sdhci-of-dwcmshc: Update DLL
and pre-change delay for rockchip platform")

Signed-off-by: Vasily Khoruzhick &lt;anarsoul@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For Rockchip platform, DLL bypass bit and start bit need to be set if
DLL is not locked.

With this change applied eMMC in my NanoPi R5S can run at 52 MHz.

Based on linux commit b75a52b0dda3 ("mmc: sdhci-of-dwcmshc: Update DLL
and pre-change delay for rockchip platform")

Signed-off-by: Vasily Khoruzhick &lt;anarsoul@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
