<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers, branch v2023.04-rc4</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers?h=v2023.04-rc4</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers?h=v2023.04-rc4'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2023-03-11T00:10:14Z</updated>
<entry>
<title>Merge https://source.denx.de/u-boot/custodians/u-boot-usb</title>
<updated>2023-03-11T00:10:14Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-03-11T00:10:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1247fc7de81d8106cdfa64ecf18aba47a6e587f3'/>
<id>urn:sha1:1247fc7de81d8106cdfa64ecf18aba47a6e587f3</id>
<content type='text'>
Two minimal Kconfig/Makefile fixes for USB.
</content>
</entry>
<entry>
<title>ARM: dts: renesas: Enable sysinfo on R-Car V3H Condor/Condor-I</title>
<updated>2023-03-10T16:46:09Z</updated>
<author>
<name>Tam Nguyen</name>
<email>tam.nguyen.xa@renesas.com</email>
</author>
<published>2023-02-27T22:58:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c8eaebb426fed1bbb7020566486b4a8f4eb0f159'/>
<id>urn:sha1:c8eaebb426fed1bbb7020566486b4a8f4eb0f159</id>
<content type='text'>
Add new sysinfo IDs for R-Car V3H Condor/Condor-I .

Enable support for sysinfo on R-Car V3H Condor/Condor-I. The sysinfo is
used e.g. to access and decode board-specific information and then in
turn used by board-info to print those information.

Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
Signed-off-by: Tam Nguyen &lt;tam.nguyen.xa@renesas.com&gt;
Signed-off-by: Hai Pham &lt;hai.pham.ud@renesas.com&gt;
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
[Marek: Drop compatible from I2C node, this is in r8a77980.dtsi already.
        Drop status = "okay" from EEPROM node.
	Add dts: tag.
	Update the commit message, note the new sysinfo IDs.
	Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
</content>
</entry>
<entry>
<title>sysinfo: rcar3: Fix Draak and Eagle board code</title>
<updated>2023-03-10T16:46:09Z</updated>
<author>
<name>Tam Nguyen</name>
<email>tam.nguyen.xa@renesas.com</email>
</author>
<published>2023-02-27T22:58:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b791b9cf5500b589df5f8b227a6320bf34ba081c'/>
<id>urn:sha1:b791b9cf5500b589df5f8b227a6320bf34ba081c</id>
<content type='text'>
Correct the board code ID based on the hardware documentation

Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
Signed-off-by: Tam Nguyen &lt;tam.nguyen.xa@renesas.com&gt;
Signed-off-by: Hai Pham &lt;hai.pham.ud@renesas.com&gt;
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: renesas: Drop non-existent PFC info table entries</title>
<updated>2023-03-10T16:46:09Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2023-02-28T06:25:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ce4681721570494574beff5f47df3d35d5e9aa10'/>
<id>urn:sha1:ce4681721570494574beff5f47df3d35d5e9aa10</id>
<content type='text'>
Remove PFC info table entries which are never instantiated,
since there are no drivers for those. No functional change.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>clk: renesas: Always select DM_RESET to prevent inobvious failure of rst_gen3 subdriver</title>
<updated>2023-03-10T16:46:09Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2023-02-28T21:16:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3efdf01fa49a24cc2f1139d67f2e1e5cd43cf882'/>
<id>urn:sha1:3efdf01fa49a24cc2f1139d67f2e1e5cd43cf882</id>
<content type='text'>
The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3.
The former depends on the clock framework, which is always enabled
in this context of clock framework driver, while the later depends
on reset framework which may not always be enabled.

Ensure the reset framework is also always enabled to prevent inobvious
early boot time bind failure of the CPG driver, which leads to system
showing no activity and is difficult to debug.

Note that one possible approach to debug this is to use CONFIG_DEBUG_UART
and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c .

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>mmc: renesas-sdhi: Add proper probe error fail path</title>
<updated>2023-03-10T16:45:47Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2023-02-27T22:49:28Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f20a61af4209785721bdee96131785d9dc24698d'/>
<id>urn:sha1:f20a61af4209785721bdee96131785d9dc24698d</id>
<content type='text'>
In case one of the calls in probe fail, trigger a fail path and
undo all the steps done in probe until the point of failure.
The current implementation failed to stop controller clock and
free claimed clock, so fix that. Furthermore, print return code
in error prints for easier debugging.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>mmc: renesas-sdhi: Always configure default SDnH clock rate to 800 MHz</title>
<updated>2023-03-10T16:45:47Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2023-02-27T22:49:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6ddffa89cb8396bf043adcc5090e8b1a9b1d0246'/>
<id>urn:sha1:6ddffa89cb8396bf043adcc5090e8b1a9b1d0246</id>
<content type='text'>
The prior stage bootloader might have left the SDnCKCR register in completely
arbitrary state before passing control to U-Boot, which includes the register
being populated with incorrect values. Currently the SDHI driver will attempt
to use clock framework to configure SDn clock, which may fail in case SDnCKCR
contains invalid values for the SDnH clock, because the clock framework would
not be able to determine SDnH clock rate and would get -EINVAL instead, which
in turn would not allow the clock framework to determine the correct SDn clock
divider ratio.

This failure occurs specifically in case SDnCKCR reads back 0x209 .

Correct the problem by first setting default SDnH clock rate to 800 MHz, thus
assuring the SDnCKCR SDnH bits are correct, and only afterward set up the SDn
clock rate to default 200 MHz.

Note that the SDHI driver may reconfigure SDnH clock later based on IOS
settings obtained from the attached card, the 800 MHz set up here is only
the default value.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>usb: move CONFIG_USB_HUB_DEBOUNCE_TIMEOUT to USB</title>
<updated>2023-03-10T16:31:31Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2023-01-25T18:40:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4042ce73c8bee9077d80a42b27aa21f98636b780'/>
<id>urn:sha1:4042ce73c8bee9077d80a42b27aa21f98636b780</id>
<content type='text'>
This configuration setting is only relevant if the board supports USB.
It should not be in the main menu but in the USB menu.

The setting is only relevant in USB host mode.

Fixes: 5454dea3137d ("usb: hub: allow to increase HUB_DEBOUNCE_TIMEOUT")
Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</content>
</entry>
<entry>
<title>sandbox: fix building with CONFIG_SPL_TIMER=y</title>
<updated>2023-03-01T18:22:40Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2023-02-22T00:39:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d22c69524966b6d65d98476acb7fda827207e10d'/>
<id>urn:sha1:d22c69524966b6d65d98476acb7fda827207e10d</id>
<content type='text'>
Building sandbox_defconfig with CONFIG_SPL_TIMER=y results in an error

    include/dm/platdata.h:63:33: error: static assertion failed:
    "Cannot use U_BOOT_DRVINFO with of-platdata.
    Please use devicetree instead"

Add a missing condition in the sandbox driver.

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm64: a37xx: pinctrl: probe after binding</title>
<updated>2023-03-01T18:22:27Z</updated>
<author>
<name>Robert Marko</name>
<email>robert.marko@sartura.hr</email>
</author>
<published>2023-01-17T14:08:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1de76a4535a2d617adeb05070d265e2826af3ad6'/>
<id>urn:sha1:1de76a4535a2d617adeb05070d265e2826af3ad6</id>
<content type='text'>
Currently, pinctrl drivers are getting probed during post-bind, however
that is being reverted, and on A37XX pinctrl driver is the one that
registers the GPIO driver during the probe.

So, if the pinctrl driver doesn't get probed GPIO-s won't get registered
and thus they cannot be used.

This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s
and without them being registered networking won't work as it only has
one SFP slot and the TX disable GPIO is on the SB controller.

So, lets just add a flag only to A37XX driver to probe after binding
in order for the GPIO driver to always get registered.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
</feed>
