u-boot.git/drivers, branch v2023.07

pinctrl: rockchip: Fix Data Abort exception in SPL

2023-06-29T10:42:58+00:00

Using CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y and CONFIG_OF_LIVE=y triggers
a Data Abort exception from unaligned memory access when the pinctrl
driver iterate node properties, e.g. for UART2 on RK3568.

  setting mux of GPIO0-24 to 1
  setting mux of GPIO0-24 to 1
  "Synchronous Abort" handler, esr 0x96000021
  elr: 000000000000e554 lr : 000000000000e54c
  x 0: 0000000000000a5c x 1: 0000000000000a5c
  x 2: 0000000000000007 x 3: 0000000000000065
  x 4: 0000000000000007 x 5: 0000000000022d4e
  x 6: 0000000000000a7c x 7: 00000000000227a4
  x 8: 0000000000021cf0 x 9: 0000000000000a7c
  x10: 0000000000021cf0 x11: 0000000000021cf0
  x12: 00000000003fda1c x13: 0000000000000007
  x14: 00000000003fd9ec x15: 000000000001c0ff
  x16: 0000000007000000 x17: 00000000fdccd028
  x18: 00000000003fde20 x19: 0000000000000018
  x20: 0000000000020670 x21: 0000000000000000
  x22: 00000000003fdb00 x23: 00000000003fef90
  x24: 0000000000020688 x25: 0000000000000000
  x26: 0000000000000001 x27: 00000000003ffc50
  x28: 0000000000000000 x29: 00000000003fda60

  Code: b94083e1 97ffd508 93407c01 37f81260 (f9401038)
  Resetting CPU ...

Fix this by replacing the loop to access node properties with use of
ofnode_for_each_prop instead of the current ifdef.

Also continue to next prop instead of aborting at first sign of an
unknown property.

This fixes the Data Abort exception and also pinconf of e.g. pull and
drive in SPL, e.g. for UART2 on RK3568.

  setting mux of GPIO0-24 to 1
  setting mux of GPIO0-24 to 1
  setting pull of GPIO0-24 to 5
  setting mux of GPIO0-25 to 1
  setting mux of GPIO0-25 to 1
  setting pull of GPIO0-25 to 5

Fixes: e7ae4cf27a6d ("pinctrl: rockchip: Add common rockchip pinctrl driver")
Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang

phy: rockchip: inno-usb2: fix phy reg=0 case

2023-06-29T10:31:48+00:00

The support for #address-cells=2 has a loophole: if the reg is actually 0,
but the #address-cells is actually 1, like in such case below:

syscon {
	#address-cells = <1>;

	phy {
		reg = <0 0x10>;
	};
};

then the second u32 of the 'reg' is the size, not the address.

The code should check for the parent's #address-cells value, and not
assume that if the first u32 is 0, then the #address-cells is 2, and the
reg property is something like
	reg = <0 0xff00 0x10>;

Fixed this by looking for the #address-cells value and retrieving the
reg address only if this is ==2.
To avoid breaking anything I also kept the check `if reg==0` as some DT's
may have a wrong #address-cells as parent and even if this commit is
correct, it might break the existing wrong device-trees.

Fixes: d538efb9adcf ("phy: rockchip: inno-usb2: Add support #address_cells = 2")
Signed-off-by: Eugen Hristev 
Reviewed-by: Kever Yang

usb: dwc2: Fix the write to W1C fields in HPRT register

2023-06-21T11:15:58+00:00

Fix the write to the HPRT register which treat W1C fields
as if they were mere RW. This leads to unintended clearing of such fields

This bug was found during the testing on Simics model. Referring to
specification DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG)
Databook (3.30a)"5.3.4.8 Host Port Control and Status Register (HPRT)", the
HPRT.PrtPwr is cleared by this mistake. In the Linux driver (contrary to
U-Boot), HPRT is always read using dwc2_read_hprt0 helper function which
clears W1C bits. So after write back those bits are zeroes.

Signed-off-by: Teik Heng Chong

net: rtl8169: add depends on PCI

2023-06-14T16:56:10+00:00

The rtl8169 driver uses calls to dm_pci_bus_to_phys,
which are compiled under CONFIG_PCI.

Without CONFIG_PCI, this happens:

drivers/net/rtl8169.o: in function `rtl_recv_common':
drivers/net/rtl8169.c:555: undefined reference to `dm_pci_bus_to_phys'

It is only natural that this driver depends on CONFIG_PCI then.
The device does not work connected in another way anyway, and the driver
does not assume anything else at this moment.

Signed-off-by: Eugen Hristev 
Reviewed-by: Ramon Fried

Merge https://source.denx.de/u-boot/custodians/u-boot-usb

2023-06-08T22:23:06+00:00

pinctrl: renesas: r8a779a0: Remove incorrect AVB[01] pinmux configuration

2023-06-08T20:22:38+00:00

AVB[01]_{MAGIC,MDC,MDIO,TXCREFCLK} are registered as both
PINMUX_SINGLE(fn) and PINMUX_IPSR_GPSR(fn) in the pinmux_data array.

The latter are correct, hence remove the former.
Without this fix, the Ethernet PHY is not operational on the MDIO bus.

Ported from Linux kernel commit a145c9a8674ac8fbfa1595276e1b6cbfc5139038 .

Signed-off-by: Hai Pham 
Signed-off-by: LUU HOAI 
Fixes: 741a7370fc3b8b54 ("pinctrl: renesas: Initial R8A779A0 (V3U) PFC support")
Signed-off-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/6fd217b71e83ba9a8157513ed671a1fa218b23b6.1674824958.git.geert+renesas@glider.be
---
Cc: Geert Uytterhoeven 
Cc: Hai Pham 
Cc: LUU HOAI 
Cc: Marek Vasut

usb: musb-new: sunxi: remove unused define

2023-06-08T19:57:01+00:00

This is a remnant from when the USB controller driver managed
the reset signal itself. A patch from the very end of 2018 changed
this driver to delegate reset (and clock) management to the proper
control unit driver, but left this unused define behind.

Signed-off-by: Sam Edwards 
Reviewed-by: Marek Vasut

phy: rockchip-inno-usb2: Implement clock operations for usb2phy clock

2023-06-07T21:41:47+00:00

This clock doesn't seem needed but appears in a phandle list used by
ehci-generic.c to bulk enable it. The phandle list comes from linux,
where it is needed for suspend/resume to work [1].

My tests give the same results with or without this patch, but Marek
Vasut found it weird to declare an empty clk_ops [2].

So I adapted the code from linux 6.1-rc8 so that it hopefully works
if it ever has some user. For now, without real use, it seems to
at least not give any errors when called.

Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
      [2] https://patchwork.ozlabs.org/project/uboot/patch/Y5IWpjYLB4aXMy9o@localhost/

Cc: Simon Glass 
Cc: Philipp Tomsich 
Cc: Kever Yang 
Cc: Lukasz Majewski 
Cc: Sean Anderson 
Cc: Marek Vasut 
Cc: Christoph Fritz 
Cc: Jagan Teki 

Signed-off-by: Xavier Drudis Ferran 
Reviewed-by: Kever Yang 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # rk3399, rk3328, rv1126

phy: rockchip-inno-usb2: Add usb2phy clock provider of 480MHz clock

2023-06-07T21:41:47+00:00

arch/arm/dts/rk3399.dtsi has a node

  usb_host0_ehci: usb@fe380000 {
       compatible = "generic-ehci";

with clocks:

       clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
                <&u2phy0>;

The first 2 refer to nodes with class UCLASS_CLK, but &u2phy0
has class UCLASS_PHY.

  u2phy0: usb2phy@e450 {
       compatible = "rockchip,rk3399-usb2phy";

Since clk_get_bulk() only looks for devices with UCLASS_CLK,
it fails with -ENODEV and then ehci_usb_probe() aborts.

The consequence is peripherals connected to a USB 2 port (e.g. in a
Rock Pi 4 the white port, nearer the edge) not being detected.
They're detected if CONFIG_USB_OHCI_GENERIC is selected in Kconfig,
because ohci_usb_probe() does not abort when one clk_get_by_index()
fails, but then they work in USB 1 mode.

rk3399.dtsi comes from linux and the  u2phy0 was added[1] to the clock
list in:

    commit b5d1c57299734f5b54035ef2e61706b83041f20c
    Author: William wu 
    Date:   Wed Dec 21 18:41:05 2016 +0800

    arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399

    We found that the suspend process was blocked when it run into
    ehci/ohci module due to clk-480m of usb2-phy was disabled.
    [...]

Suspend concerns don't apply to U-Boot, and the problem with U-Boot
failing to probe EHCI doesn't apply to linux, because in linux
rockchip_usb2phy_clk480m_register makes u2phy0 a proper clock provider
when called by rockchip_usb2phy_probe().

So I can think of a few alternative solutions:

1- Change ehci_usb_probe() to make it more similar to
   ohci_usb_probe(), and survive failure to get one clock. Looks a
   little harder, and I don't know whether it could break something if
   it ignored a clock that was important for something else than
   suspend.

2- Change rk3399.dtsi effectively reverting the linux commit
   b5d1c57299734f5b54035ef2e61706b83041f20c. This dealigns the .dtsi
   from linux and seems fragile at the next synchronisation.

3- Change the clock list in rk3399-u-boot.dtsi or somewhere else.
   This survives .dts* sync but may survive "too much" and miss some
   change from linux that we might want.

4- Enable CONFIG_USB_OHCI_GENERIC and use the ports in USB 1 mode.
   This would need to be made for all boards using rk3399.  In a
   simple test reading one file from USB storage it gave 769.5 KiB/s
   instead of 20.5 MiB/s with solution 2.

5- Trying to replicate linux and have usb2phy somehow provide a clk,
   or have a separate clock device for usb2phy in addition to the phy
   device.

This patch tries to implement option 5 as Marek Vasut requested in
December 5th.  Options 1 and 3 didn't get through [2][3].

It just registers usb2phy as a clock driver (device_bind_driver()
didn't work but device_bind_driver_to_node() did), without any
specific operations, so that ehci-generic.c finds it and is happy. It
worked in my tests on a Rock Pi 4 B+ (rk3399).

Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
      [2] https://patchwork.ozlabs.org/project/uboot/patch/20220701185959.GC1700@begut/
      [3] https://patchwork.ozlabs.org/project/uboot/patch/Y44+ayJfUlI08ptM@localhost/

Cc: Simon Glass 
Cc: Philipp Tomsich 
Cc: Kever Yang 
Cc: Lukasz Majewski 
Cc: Sean Anderson 
Cc: Marek Vasut 
Cc: Christoph Fritz 
Cc: Jagan Teki 

Signed-off-by: Xavier Drudis Ferran 
Reviewed-by: Kever Yang 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # rk3399, rk3328, rv1126

usb: musb-new: sunxi: fix error check

2023-06-07T21:38:51+00:00

The `musb_register` function returns some ERR_PTR(...) on failure,
not NULL, so update the check here appropriately.

Signed-off-by: Sam Edwards 
Reviewed-by: Marek Vasut