u-boot.git/drivers, branch v2023.07-rc4

Merge https://source.denx.de/u-boot/custodians/u-boot-usb

2023-06-08T22:23:06+00:00

pinctrl: renesas: r8a779a0: Remove incorrect AVB[01] pinmux configuration

2023-06-08T20:22:38+00:00

AVB[01]_{MAGIC,MDC,MDIO,TXCREFCLK} are registered as both
PINMUX_SINGLE(fn) and PINMUX_IPSR_GPSR(fn) in the pinmux_data array.

The latter are correct, hence remove the former.
Without this fix, the Ethernet PHY is not operational on the MDIO bus.

Ported from Linux kernel commit a145c9a8674ac8fbfa1595276e1b6cbfc5139038 .

Signed-off-by: Hai Pham 
Signed-off-by: LUU HOAI 
Fixes: 741a7370fc3b8b54 ("pinctrl: renesas: Initial R8A779A0 (V3U) PFC support")
Signed-off-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/6fd217b71e83ba9a8157513ed671a1fa218b23b6.1674824958.git.geert+renesas@glider.be
---
Cc: Geert Uytterhoeven 
Cc: Hai Pham 
Cc: LUU HOAI 
Cc: Marek Vasut

usb: musb-new: sunxi: remove unused define

2023-06-08T19:57:01+00:00

This is a remnant from when the USB controller driver managed
the reset signal itself. A patch from the very end of 2018 changed
this driver to delegate reset (and clock) management to the proper
control unit driver, but left this unused define behind.

Signed-off-by: Sam Edwards 
Reviewed-by: Marek Vasut

phy: rockchip-inno-usb2: Implement clock operations for usb2phy clock

2023-06-07T21:41:47+00:00

This clock doesn't seem needed but appears in a phandle list used by
ehci-generic.c to bulk enable it. The phandle list comes from linux,
where it is needed for suspend/resume to work [1].

My tests give the same results with or without this patch, but Marek
Vasut found it weird to declare an empty clk_ops [2].

So I adapted the code from linux 6.1-rc8 so that it hopefully works
if it ever has some user. For now, without real use, it seems to
at least not give any errors when called.

Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
      [2] https://patchwork.ozlabs.org/project/uboot/patch/Y5IWpjYLB4aXMy9o@localhost/

Cc: Simon Glass 
Cc: Philipp Tomsich 
Cc: Kever Yang 
Cc: Lukasz Majewski 
Cc: Sean Anderson 
Cc: Marek Vasut 
Cc: Christoph Fritz 
Cc: Jagan Teki 

Signed-off-by: Xavier Drudis Ferran 
Reviewed-by: Kever Yang 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # rk3399, rk3328, rv1126

phy: rockchip-inno-usb2: Add usb2phy clock provider of 480MHz clock

2023-06-07T21:41:47+00:00

arch/arm/dts/rk3399.dtsi has a node

  usb_host0_ehci: usb@fe380000 {
       compatible = "generic-ehci";

with clocks:

       clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
                <&u2phy0>;

The first 2 refer to nodes with class UCLASS_CLK, but &u2phy0
has class UCLASS_PHY.

  u2phy0: usb2phy@e450 {
       compatible = "rockchip,rk3399-usb2phy";

Since clk_get_bulk() only looks for devices with UCLASS_CLK,
it fails with -ENODEV and then ehci_usb_probe() aborts.

The consequence is peripherals connected to a USB 2 port (e.g. in a
Rock Pi 4 the white port, nearer the edge) not being detected.
They're detected if CONFIG_USB_OHCI_GENERIC is selected in Kconfig,
because ohci_usb_probe() does not abort when one clk_get_by_index()
fails, but then they work in USB 1 mode.

rk3399.dtsi comes from linux and the  u2phy0 was added[1] to the clock
list in:

    commit b5d1c57299734f5b54035ef2e61706b83041f20c
    Author: William wu 
    Date:   Wed Dec 21 18:41:05 2016 +0800

    arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399

    We found that the suspend process was blocked when it run into
    ehci/ohci module due to clk-480m of usb2-phy was disabled.
    [...]

Suspend concerns don't apply to U-Boot, and the problem with U-Boot
failing to probe EHCI doesn't apply to linux, because in linux
rockchip_usb2phy_clk480m_register makes u2phy0 a proper clock provider
when called by rockchip_usb2phy_probe().

So I can think of a few alternative solutions:

1- Change ehci_usb_probe() to make it more similar to
   ohci_usb_probe(), and survive failure to get one clock. Looks a
   little harder, and I don't know whether it could break something if
   it ignored a clock that was important for something else than
   suspend.

2- Change rk3399.dtsi effectively reverting the linux commit
   b5d1c57299734f5b54035ef2e61706b83041f20c. This dealigns the .dtsi
   from linux and seems fragile at the next synchronisation.

3- Change the clock list in rk3399-u-boot.dtsi or somewhere else.
   This survives .dts* sync but may survive "too much" and miss some
   change from linux that we might want.

4- Enable CONFIG_USB_OHCI_GENERIC and use the ports in USB 1 mode.
   This would need to be made for all boards using rk3399.  In a
   simple test reading one file from USB storage it gave 769.5 KiB/s
   instead of 20.5 MiB/s with solution 2.

5- Trying to replicate linux and have usb2phy somehow provide a clk,
   or have a separate clock device for usb2phy in addition to the phy
   device.

This patch tries to implement option 5 as Marek Vasut requested in
December 5th.  Options 1 and 3 didn't get through [2][3].

It just registers usb2phy as a clock driver (device_bind_driver()
didn't work but device_bind_driver_to_node() did), without any
specific operations, so that ehci-generic.c finds it and is happy. It
worked in my tests on a Rock Pi 4 B+ (rk3399).

Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
      [2] https://patchwork.ozlabs.org/project/uboot/patch/20220701185959.GC1700@begut/
      [3] https://patchwork.ozlabs.org/project/uboot/patch/Y44+ayJfUlI08ptM@localhost/

Cc: Simon Glass 
Cc: Philipp Tomsich 
Cc: Kever Yang 
Cc: Lukasz Majewski 
Cc: Sean Anderson 
Cc: Marek Vasut 
Cc: Christoph Fritz 
Cc: Jagan Teki 

Signed-off-by: Xavier Drudis Ferran 
Reviewed-by: Kever Yang 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # rk3399, rk3328, rv1126

usb: musb-new: sunxi: fix error check

2023-06-07T21:38:51+00:00

The `musb_register` function returns some ERR_PTR(...) on failure,
not NULL, so update the check here appropriately.

Signed-off-by: Sam Edwards 
Reviewed-by: Marek Vasut

serial: meson: fix meson_serial_pending() tx logic

2023-06-07T08:09:20+00:00

According to the dm_serial_ops documentation, pending() should:
> @return number of waiting characters, 0 for none, -ve on error

And:
> It is acceptable to return 1 if an indeterminant number
> of characters is waiting.

With the current implementation, we have:
* FIFO is full           -> pending() returns 0
* FIFO is partially used -> pending() returns 1
* FIFO is empty          -> pending() returns 1

This is not the same as what the documentation requires.

Moreover, since [1], arm reset now flushes all console devices
(including serial) before the cpu gets reset.
Because of the flawed logic:

  => reset # user calls reset
  flush() is called
  _serial_flush() is called
  ops->pending(dev, false) # never returns false
  # board hangs indefinitely without resetting.

Fix it by using AML_UART_TX_EMPTY instead of AML_UART_TX_FULL.

[1] commit c5f4cdb8eb60 ("console: Use flush() before panic and reset"),

Signed-off-by: Mattijs Korpershoek 
Acked-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20230606-fix-meson-serial-pending-v1-1-6a54d4a01f76@baylibre.com
Signed-off-by: Neil Armstrong

I2C: cdns: Fix broken retry mechanism on arbitration lost.

2023-06-05T04:54:25+00:00

In the current implementation, in case of I2C arbitration lost, a retry is
attempted; the message counter and pointer are reset to the original values
and the I2C xfer process is restart from the beginning.

However the message counter and message pointer are respectively
decremented and incremented by one before attempting any transfer, causing
the 1st transfer not to be actually retried (in case of a single transfer,
nothing is actually retried at all).

This patch fixes this: in case of retry, the 1st transfer is also retried.

Tested on a ZynqMP Kria board, with upstream older u-boot, but the involved
file and underlying logic seem basically the same.

Signed-off-by: Andrea Merello

i2c: rockchip: De-initialize the bus after start bit failure

2023-06-05T04:52:46+00:00

Failure can happen when i2c is used without initializing pinctrl properly,
which U-Boot happily allows in SPL. Without this fix, further I2C access would
fail, even after proper pinctrl initialization.

Signed-off-by: Ondrej Jirman 
Cc: Heiko Schocher 
Reviewed-by: Kever Yang 
Reviewed-by: Heiko Schocher

pci: apple: Add support for M2 Pro/Max

2023-05-30T19:13:44+00:00

The PCIe controller on the M2 Pro/Max is different from the one
found on earlier Apple SoCs.  Some registers moved and te meaning
of the bits in some other registers changed.  But they are still
similar enough to handle both controllers in the same driver.

Signed-off-by: Mark Kettenis