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<title>u-boot.git/drivers, branch v2023.07.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers?h=v2023.07.01</id>
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<updated>2023-07-07T20:47:15Z</updated>
<entry>
<title>sysreset: Change Kconfig GPIO dependency</title>
<updated>2023-07-07T20:47:15Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2023-07-04T12:05:13Z</published>
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<id>urn:sha1:99a0532a2d09edac8d8cf59deb68e03f3275e494</id>
<content type='text'>
DM_GPIO depends on GPIO to be enabled but select will cause that DM_GPIO is
selected without GPIO which ends up in compilation error:
undefined reference to `dm_gpio_set_value'
undefined reference to `dm_gpio_get_value'
undefined reference to `dm_gpio_free'
undefined reference to `gpio_request_by_name'

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
[trini: Fix configs which had relied on these select's]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-usb into next</title>
<updated>2023-07-06T17:23:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-07-06T17:23:36Z</published>
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<id>urn:sha1:56c7fac8ad89955d3e5d08864bbd1343a058bf4b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>clk: starfive: pll: Fix to use postdiv1_mask</title>
<updated>2023-07-06T09:28:08Z</updated>
<author>
<name>Hoegeun Kwon</name>
<email>hoegeun.kwon@samsung.com</email>
</author>
<published>2023-06-28T10:19:49Z</published>
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<id>urn:sha1:422fc299df9b873e7e485db08621e5fb499c6a8f</id>
<content type='text'>
There is a problem that the rates of PLL0 and PLL1 are set incorrectly
because the postdiv1_mask value is incorrectly entered when setting
the pll clk reg. Modify postdiv1's mask value to be put correctly.

Signed-off-by: Hoegeun Kwon &lt;hoegeun.kwon@samsung.com&gt;
Reviewed-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>clk: sifive: only build sifive-prci.o for CONFIG_CLK_SIFIVE_PRCI</title>
<updated>2023-07-06T09:28:08Z</updated>
<author>
<name>Ben Dooks</name>
<email>ben.dooks@sifive.com</email>
</author>
<published>2023-05-09T13:50:05Z</published>
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<id>urn:sha1:c29cc110d7c2486c0b71edaccd8bc61cb77385a4</id>
<content type='text'>
If we're building non FU540/FU740 SoC drivers, then the sifive-prci.o
is not needed. Only build this when CONFIG_CLK_SIFIVE_PRCI is selected.

Signed-off-by: Ben Dooks &lt;ben.dooks@sifive.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v2023.07-rc6' into next</title>
<updated>2023-07-05T15:28:55Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-07-05T15:28:55Z</published>
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<id>urn:sha1:e80f4079b3a3db0961b73fa7a96e6c90242d8d25</id>
<content type='text'>
Prepare v2023.07-rc6
</content>
</entry>
<entry>
<title>regulator: handle different error codes in regulator_set_enable_if_allowed</title>
<updated>2023-07-04T02:21:12Z</updated>
<author>
<name>Eugen Hristev</name>
<email>eugen.hristev@collabora.com</email>
</author>
<published>2023-04-19T13:45:26Z</published>
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<id>urn:sha1:8202bc29454cfdd5839058e4b79c36a3fbb221cf</id>
<content type='text'>
The regulator core can return different codes which are not considered
a real error for this function.
Return success in such cases.

Signed-off-by: Eugen Hristev &lt;eugen.hristev@collabora.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>regulator: rename dev_pdata to plat</title>
<updated>2023-07-04T02:21:07Z</updated>
<author>
<name>Eugen Hristev</name>
<email>eugen.hristev@collabora.com</email>
</author>
<published>2023-04-19T13:45:25Z</published>
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<id>urn:sha1:29fca9f23a3b730cbf91c18617e25d9d8e3a26b7</id>
<content type='text'>
Simplify the subsystem by renaming `dev_pdata` to just `plat`.
No functional change, just trivial renaming.

Suggested-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Eugen Hristev &lt;eugen.hristev@collabora.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>regulator: implement basic reference counter</title>
<updated>2023-07-04T02:20:56Z</updated>
<author>
<name>Eugen Hristev</name>
<email>eugen.hristev@collabora.com</email>
</author>
<published>2023-04-19T13:45:24Z</published>
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<id>urn:sha1:4fcba5d556b4224ad65a249801e4c9594d1054e8</id>
<content type='text'>
Some devices share a regulator supply, when the first one will request
regulator disable, the second device will have it's supply cut off before
graciously shutting down. Hence there will be timeouts and other failed
operations.
Implement a reference counter mechanism similar with what is done in
Linux, to keep track of enable and disable requests, and only disable the
regulator when the last of the consumers has requested shutdown.

Signed-off-by: Eugen Hristev &lt;eugen.hristev@collabora.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>usb: dwc3-generic: Ensure reset GPIO is configured as an output</title>
<updated>2023-07-03T08:46:34Z</updated>
<author>
<name>Peter Korsgaard</name>
<email>peter@korsgaard.com</email>
</author>
<published>2023-06-28T12:26:48Z</published>
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<id>urn:sha1:d266d4b63873c2176677a79d48faeb9db7d4acdd</id>
<content type='text'>
GPIOD_ACTIVE_LOW is not enough to configure a GPIO as an output, we need
GPIOD_IS_OUT as well.

Fixes: b252d79b0936d60b ("usb: dwc3: Add support to reset usb ULPI phy")
Signed-off-by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: rockchip: Fix Data Abort exception in SPL</title>
<updated>2023-06-29T10:42:58Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2023-06-08T10:59:38Z</published>
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<id>urn:sha1:63348d61a878187a368c0638833efbaf76fc89f9</id>
<content type='text'>
Using CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y and CONFIG_OF_LIVE=y triggers
a Data Abort exception from unaligned memory access when the pinctrl
driver iterate node properties, e.g. for UART2 on RK3568.

  setting mux of GPIO0-24 to 1
  setting mux of GPIO0-24 to 1
  "Synchronous Abort" handler, esr 0x96000021
  elr: 000000000000e554 lr : 000000000000e54c
  x 0: 0000000000000a5c x 1: 0000000000000a5c
  x 2: 0000000000000007 x 3: 0000000000000065
  x 4: 0000000000000007 x 5: 0000000000022d4e
  x 6: 0000000000000a7c x 7: 00000000000227a4
  x 8: 0000000000021cf0 x 9: 0000000000000a7c
  x10: 0000000000021cf0 x11: 0000000000021cf0
  x12: 00000000003fda1c x13: 0000000000000007
  x14: 00000000003fd9ec x15: 000000000001c0ff
  x16: 0000000007000000 x17: 00000000fdccd028
  x18: 00000000003fde20 x19: 0000000000000018
  x20: 0000000000020670 x21: 0000000000000000
  x22: 00000000003fdb00 x23: 00000000003fef90
  x24: 0000000000020688 x25: 0000000000000000
  x26: 0000000000000001 x27: 00000000003ffc50
  x28: 0000000000000000 x29: 00000000003fda60

  Code: b94083e1 97ffd508 93407c01 37f81260 (f9401038)
  Resetting CPU ...

Fix this by replacing the loop to access node properties with use of
ofnode_for_each_prop instead of the current ifdef.

Also continue to next prop instead of aborting at first sign of an
unknown property.

This fixes the Data Abort exception and also pinconf of e.g. pull and
drive in SPL, e.g. for UART2 on RK3568.

  setting mux of GPIO0-24 to 1
  setting mux of GPIO0-24 to 1
  setting pull of GPIO0-24 to 5
  setting mux of GPIO0-25 to 1
  setting mux of GPIO0-25 to 1
  setting pull of GPIO0-25 to 5

Fixes: e7ae4cf27a6d ("pinctrl: rockchip: Add common rockchip pinctrl driver")
Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
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