u-boot.git/drivers, branch v2024.01

spi: npcm_pspi: Fix the wrong clock divider calculation

2023-12-26T19:41:46+00:00

Fix the wrong clock divider calculation.

Signed-off-by: Jim Liu

test: dm: clk_ccf: test ccf_clk_ops

2023-12-15T18:50:44+00:00

Assign ccf_clk_ops to .ops of clk_ccf driver so that it can act as an
clk provider. Also add "#clock-cells=<1>" to its device tree node.

Add "i2c_root" to clk_test in the device tree and driver for testing.

Get "i2c_root" clock in CCF unit tests and add tests for it.

Signed-off-by: Yang Xiwen 
Reviewed-by: Sean Anderson 
Link: https://lore.kernel.org/r/20231111-enable_count-v3-2-08a821892fa9@outlook.com

clk: Check that composite clock's div has set_rate()

2023-12-15T17:32:00+00:00

It's possible for composite clocks to have a divider that does not
implement set_rate() operation. For example, sandbox_clk_composite()
registers composite clock with a divider that only has get_rate().
Currently clk_composite_set_rate() only checks thate rate_ops are
present, so for sandbox it will cause NULL dereference during
clk_set_rate().

This patch adds rate_ops->set_rate check tp clk_composite_set_rate().

Signed-off-by: Igor Prusov 
Reviewed-by: Sean Anderson 
Link: https://lore.kernel.org/r/20231205232334.2931-2-ivprusov@salutedevices.com

clk: get correct ops for clk_enable() and clk_disable()

2023-12-15T17:31:47+00:00

assign clk_dev_ops(clkp->dev) to ops to ensure correct clk operations
are called on clocks.

This fixes the incorrect enable_count issue as described in [1].

[1]: https://lore.kernel.org/all/SEZPR06MB695927A6DEEEF8489A06897396A7A@SEZPR06MB6959.apcprd06.prod.outlook.com/

Signed-off-by: Yang Xiwen 
Reviewed-by: Sean Anderson 
Link: https://lore.kernel.org/r/20231111-enable_count-v2-2-20e3728600b5@outlook.com

clk: check parent_name in clk_register to avoid confusing log_error() output

2023-12-15T17:31:15+00:00

For some gate clocks and fixed clocks without a parent, calling
clk_register will print an useless error message indicating that parent
is missing. Fix that by gaurding log_xxx() with an if-statement.

Signed-off-by: Yang Xiwen 
Suggested-by: Sean Anderson 
Reviewed-by: Sean Anderson 
Link: https://lore.kernel.org/r/20230807-clk-fix-v2-1-0b688e21fb4e@outlook.com

ddr: imx: Add 3600 MTps rate support

2023-12-14T18:29:08+00:00

Add PLL settings for DDR 3600 MTps . This is very similar to 3200 MTps
PLL setting, except the divider is not 9 but 8 .

Signed-off-by: Marek Vasut 
Reviewed-by: Fabio Estevam

ddr: imx: Handle 3734 in addition to 3733 and 3732 MTps rates

2023-12-14T18:29:08+00:00

The new MX8M DDR tool 3.31 now generates a programming file which uses
data rate 3734 instead of 3733 or 3732 . Handle another rounding option .

Signed-off-by: Marek Vasut 
Reviewed-by: Fabio Estevam

drivers: misc: Kconfig: Fix SPL_FS_LOADER prompt

2023-12-13T14:57:02+00:00

Both FS_LOADER and SPL_FS_LOADER have the same menu prompt.
To avoid confusion, make prompt for SPL_FS_LOADER different.

Signed-off-by: Alexander Gendin 
Reviewed-by: Simon Glass

Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

2023-12-09T19:35:44+00:00

- StarFive: Add StarFive watchdog driver
- VisionFive2: Support device tree overlay for VisionFive2 board
- Andes: Fix PLIC-SW setting
- RISC-V: Fix NVMe support by implying NVME_PCI for QEMU
- RISC-V: Fix binman for 64 bit format load address

sunxi: H616: remove default AXP305 selection

2023-12-06T23:09:17+00:00

The original H616 devices released about three years ago were typically
paired with an X-Powers AXP305 PMIC. Newer devices uses the smaller
AXP313, and there seem to be far more systems with this PMIC around now.

Remove the default AXP305 selection for the H616 SoC from the Kconfig,
and move the PMIC selection into the board defconfig files instead.

Signed-off-by: Andre Przywara 
Reviewed-by: Jaehoon Chung