u-boot.git/drivers, branch v2024.04-rc2 Unnamed repository; edit this file 'description' to name the repository. memory: ti-gpmc: Fix lock up at A53 SPL during NAND boot on AM64-EVM 2024-02-13T20:38:11+00:00 Roger Quadros rogerq@kernel.org 2024-02-06T14:02:51+00:00 ef473d541d8a5453ce66b3c72f7e5577a7ea6aff AM64 ES2.0 bootrom seems to enable WAIT0EDGEDETECTION interrupt. This causes a lockup at A53 SPL when accessing NAND controller or ELM registers. A good option would be to softrest GPMC block at probe but this cannot be done for AM64 as SOFTRESET bit is marked as reserved in SYSCONFIG register. Fix the issue by disabling all IRQs at probe. Signed-off-by: Roger Quadros <rogerq@kernel.org> 
AM64 ES2.0 bootrom seems to enable WAIT0EDGEDETECTION interrupt.
This causes a lockup at A53 SPL when accessing NAND controller
or ELM registers.

A good option would be to softrest GPMC block at probe
but this cannot be done for AM64 as SOFTRESET bit is marked
as reserved in SYSCONFIG register.

Fix the issue by disabling all IRQs at probe.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
net: designware: Support high memory nodes 2024-02-12T18:41:03+00:00 Nils Le Roux gilbsgilbert@gmail.com 2023-12-02T09:39:49+00:00 a5f877a0bd64af97dbc812c9a0a8d7d6a353d943 Some platforms (such as the Lichee Pi 4A) have their dwmac device addressable only in high memory space. Storing the node's base address on 32 bits is not possible in such case. Use platform's physical address type to store the base address. Signed-off-by: Nils Le Roux <gilbsgilbert@gmail.com> Cc: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> 
Some platforms (such as the Lichee Pi 4A) have their dwmac device
addressable only in high memory space. Storing the node's base address
on 32 bits is not possible in such case.

Use platform's physical address type to store the base address.

Signed-off-by: Nils Le Roux <gilbsgilbert@gmail.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Merge tag 'u-boot-imx-master-20240212' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx 2024-02-12T14:26:20+00:00 Tom Rini trini@konsulko.com 2024-02-12T14:26:20+00:00 91c37c4a20db24a4fc1d565c70035072d355cce0 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19583 - Fix the i.MX8MP SPI compatible string. - Let the SPL clock code do the configuration on Data Modul i.MX8M Plus eDM SBC. - Enable secure boot on the imx93_var_som board. 
CI:
https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19583

- Fix the i.MX8MP SPI compatible string.
- Let the SPL clock code do the configuration on Data Modul i.MX8M Plus
  eDM SBC.
- Enable secure boot on the imx93_var_som board.
spi: mxc_spi: Add imx6ul-ecspi compatible string 2024-02-10T18:15:55+00:00 Marek Vasut marex@denx.de 2024-02-08T23:59:50+00:00 05d3602737769765ff0c1e71914d521bddedfb2c Recent i.MX8MP DTs use new fsl,imx6ul-ecspi compatible string instead of the fsl,imx51-ecspi compatible string. Add the new compatible string to fix ECSPI operation on i.MX8MP. For details, see Linux: 48d74376fb68 ("arm64: dts: imx8mp: update ecspi compatible and clk") 8eb1252bbedf ("spi: imx: remove ERR009165 workaround on i.mx6ul") Fixes: 451799a6ceac ("arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4") Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de> 
Recent i.MX8MP DTs use new fsl,imx6ul-ecspi compatible string instead
of the fsl,imx51-ecspi compatible string. Add the new compatible string
to fix ECSPI operation on i.MX8MP.

For details, see Linux:
48d74376fb68 ("arm64: dts: imx8mp: update ecspi compatible and clk")
8eb1252bbedf ("spi: imx: remove ERR009165 workaround on i.mx6ul")

Fixes: 451799a6ceac ("arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4")
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
mtd: spi: renesas: Add R8A779H0 V4M support 2024-02-10T16:08:06+00:00 Hai Pham hai.pham.ud@renesas.com 2024-01-28T15:52:05+00:00 c49f9364554893d8e90fa4e9cdfc49014358f334 Support RPC SPI on R8A779H0 V4M SoC. Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
Support RPC SPI on R8A779H0 V4M SoC.

Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
pinctrl: renesas: Add R8A779H0 V4M PFC tables 2024-02-10T16:08:06+00:00 Hai Pham hai.pham.ud@renesas.com 2024-01-28T15:52:03+00:00 995a857a013d797c9b2c28c142507309a470a078 Add pinctrl tables for R8A779H0 V4M SoC. The current version of these PFC tables is imported and squashed from: https://lore.kernel.org/linux-renesas-soc/cover.1706264667.git.geert+renesas@glider.be/ Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> 
Add pinctrl tables for R8A779H0 V4M SoC.

The current version of these PFC tables is imported and squashed from:
https://lore.kernel.org/linux-renesas-soc/cover.1706264667.git.geert+renesas@glider.be/

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
clk: renesas: Implement R8A779H0 V4M PLL7 support 2024-02-10T16:08:06+00:00 Marek Vasut marek.vasut+renesas@mailbox.org 2024-01-28T15:52:02+00:00 0fb76cc0bc594ece648bc3ffc7ea01ccdbc61954 Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7 multiplier and divider values into table in R8A779H0 V4M clock driver. The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or 20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The multiplier values fitting this requirement are calculated to 120 or 100. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> 
Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7
multiplier and divider values into table in R8A779H0 V4M clock driver.

The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication
mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or
20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The
multiplier values fitting this requirement are calculated to 120 or 100.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
clk: renesas: Add R8A779H0 V4M clock tables 2024-02-10T16:08:06+00:00 Hai Pham hai.pham.ud@renesas.com 2024-01-28T15:52:01+00:00 13a014c38c16a2a2b0b890c13c31eca5e68e72c7 Add clock tables for R8A779H0 V4M SoC. The current version is imported from: https://lore.kernel.org/linux-renesas-soc/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be/ The current version still contains PLL7 extras from the previous version to provide ethernet support in U-Boot. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> 
Add clock tables for R8A779H0 V4M SoC.

The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be/
The current version still contains PLL7 extras from the
previous version to provide ethernet support in U-Boot.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Merge tag 'u-boot-imx-master-20240208' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx 2024-02-08T14:37:16+00:00 Tom Rini trini@konsulko.com 2024-02-08T14:37:16+00:00 2b51069b7c5a8331ed4a6eb641e66466f062b06a - Add USB support for phycore-imx8mp - Fix environment corruption, reset on mx6sabresd - Print reset cause on imx8 - Extend mkimage to support generating an image for i.MXRT FlexSPI - Add new apalis and colibri variants - Add support for phyBOARD-Segin-i.MX93 support - Fix when FEC is primarily used instead of EQOS on i.MX93. 
- Add USB support for phycore-imx8mp
- Fix environment corruption, reset on mx6sabresd
- Print reset cause on imx8
- Extend mkimage to support generating an image for i.MXRT FlexSPI
- Add new apalis and colibri variants
- Add support for phyBOARD-Segin-i.MX93 support
- Fix when FEC is primarily used instead of EQOS on i.MX93.
imx: scu_api: add implementation of sc_pm_reset_reason 2024-02-08T12:17:46+00:00 Igor Opaniuk igor.opaniuk@foundries.io 2024-01-31T12:49:25+00:00 0bc69a1d38f4176ec5cfaba1c41be6b7e7fd46b5 Add implementation of sc_pm_reset_reason() call for obtaining reset reason. Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io> 
Add implementation of sc_pm_reset_reason() call for obtaining
reset reason.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>