u-boot.git/drivers, branch v2024.07-rc2 Unnamed repository; edit this file 'description' to name the repository. crypto/fsl: Differentiate between CAAM and DCP in Kconfig entry 2024-05-05T14:21:39+00:00 Marek Vasut marex@denx.de 2024-04-25T23:02:09+00:00 cecb5fbb42c8b3de3d5a7df40bc01d1fdf4731d3 Differentiate between "Enable Random Number Generator support" and "Enable Random Number Generator support" in Kconfig entry, mark the first as CAAM and the second as DCP, otherwise users cannot easily decide which of the options is which and enable the correct one. Signed-off-by: Marek Vasut <marex@denx.de> 
Differentiate between "Enable Random Number Generator support" and
"Enable Random Number Generator support" in Kconfig entry, mark the
first as CAAM and the second as DCP, otherwise users cannot easily
decide which of the options is which and enable the correct one.

Signed-off-by: Marek Vasut <marex@denx.de>
crypto/fsl: Introduce SPL_FSL_CAAM_RNG 2024-05-05T14:21:39+00:00 Marek Vasut marex@denx.de 2024-04-25T23:02:08+00:00 ea701eebecca495a3b3124d322261ed896e135a1 Add SPL variant of SPL_FSL_CAAM_RNG so that the SPL_FSL_CAAM_RNG can be disabled in SPL if necessary. This may be necessary due to e.g. size constraints of the SPL. Signed-off-by: Marek Vasut <marex@denx.de> 
Add SPL variant of SPL_FSL_CAAM_RNG so that the SPL_FSL_CAAM_RNG can
be disabled in SPL if necessary. This may be necessary due to e.g.
size constraints of the SPL.

Signed-off-by: Marek Vasut <marex@denx.de>
rng: Introduce SPL_DM_RNG 2024-05-05T14:21:39+00:00 Marek Vasut marex@denx.de 2024-04-25T23:02:07+00:00 591257b05caba725eb57ceb174317ab4c7e460a7 Add SPL variant of DM_RNG so that the DM_RNG can be disabled in SPL if necessary. This may be necessary due to e.g. size constraints of the SPL. Signed-off-by: Marek Vasut <marex@denx.de> 
Add SPL variant of DM_RNG so that the DM_RNG can be disabled in SPL
if necessary. This may be necessary due to e.g. size constraints of
the SPL.

Signed-off-by: Marek Vasut <marex@denx.de>
spi: npcm_pspi: Reset HW in driver probe 2024-05-03T18:22:58+00:00 Jim Liu jim.t90615@gmail.com 2024-04-23T06:38:42+00:00 914b766a2a6b0f746b2e6fe3bf3d70881e6da610 Reset HW to clear old status and use default data mode(8-bit). Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> 
Reset HW to clear old status and use default data mode(8-bit).

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
spi: cv1800b: Add spi nor flash controller driver for cv1800b SoC 2024-05-01T16:01:18+00:00 Kongyang Liu seashell11234455@gmail.com 2024-04-20T07:08:23+00:00 6c75bea76a76e2fd21f55107e86696321e427a51 Add spi nor flash controller driver for cv1800b SoC Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Add spi nor flash controller driver for cv1800b SoC

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
board: milkv_duo: Add init code for Milk-V Duo ethernet 2024-05-01T14:46:39+00:00 Kongyang Liu seashell11234455@gmail.com 2024-04-20T07:00:27+00:00 f874dec10a68741e8d6ba5c250b7763c1d526eaa Initialize register in cv1800b ethernet phy to make it compatible with generic phy driver Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Initialize register in cv1800b ethernet phy to make it compatible with
generic phy driver

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
sysreset: cv1800b: Add sysreset driver for cv1800b SoC 2024-05-01T14:40:12+00:00 Kongyang Liu seashell11234455@gmail.com 2024-04-16T07:52:38+00:00 a4dc68cba42c6c1be5eaab6ef84d272cf42fe9ef Add sysreset driver for cv1800b SoC Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Add sysreset driver for cv1800b SoC

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
mmc: cv1800b: Add transmit tap delay config to fix write error 2024-05-01T14:40:08+00:00 Kongyang Liu seashell11234455@gmail.com 2024-04-16T07:31:05+00:00 085b3b22d32fa48804c58709ac05b69c03f572eb Currently, only the receive delay is configured while the transmit delay is not set, which may result in errors when writing to the file. This issue can be resolved by setting PHY_TX_SRC_INVERT to SDHCI_PHY_TX_RX_DLY. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> 
Currently, only the receive delay is configured while the transmit delay
is not set, which may result in errors when writing to the file. This issue
can be resolved by setting PHY_TX_SRC_INVERT to SDHCI_PHY_TX_RX_DLY.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Merge patch series "Fix MMC tuning algorithm" 2024-04-29T16:55:34+00:00 Tom Rini trini@konsulko.com 2024-04-29T16:55:34+00:00 1e4fe2186010b4a41926ec4bd906832c605bebfe Judith Mendez <jm@ti.com> says: The following patch series includes a MMC tuning algorithm fix according to the following published paper [0]. This seris also includes fixes for OTAP/ITAP delay values in j721e_4bit_sdhci_set_ios_post and for HS400 mode. For DDR52 mode, also set ENDLL=1 and call am654_sdhci_setup_dll() instead of am654_sdhci_setup_delay_chain() according to device datasheet[1]. [0] https://www.ti.com/lit/an/spract9/spract9.pdf [1] https://www.ti.com/lit/ds/symlink/am62p.pdf 
Judith Mendez <jm@ti.com> says:

The following patch series includes a MMC tuning algorithm
fix according to the following published paper [0].

This seris also includes fixes for OTAP/ITAP delay values
in j721e_4bit_sdhci_set_ios_post and for HS400 mode.

For DDR52 mode, also set ENDLL=1 and call am654_sdhci_setup_dll()
instead of am654_sdhci_setup_delay_chain() according to
device datasheet[1].

[0] https://www.ti.com/lit/an/spract9/spract9.pdf
[1] https://www.ti.com/lit/ds/symlink/am62p.pdf
mmc: am654_sdhci: Fix ITAPDLY for HS400 timing 2024-04-29T16:55:27+00:00 Judith Mendez jm@ti.com 2024-04-18T19:01:00+00:00 f13a830e6e4ad884069e25c7cd2dc333b474da98 At HS400 mode the ITAPDLY value is that from High Speed mode which is incorrect and may cause boot failures. The ITAPDLY for HS400 speed mode should be the same as ITAPDLY as HS200 timing after tuning is executed. Add the functionality to save ITAPDLY from HS200 tuning and save as HS400 ITAPDLY. Fixes: c964447ea3d6 ("mmc: am654_sdhci: Add support for input tap delay") Signed-off-by: Judith Mendez <jm@ti.com> 
At HS400 mode the ITAPDLY value is that from High Speed mode
which is incorrect and may cause boot failures.

The ITAPDLY for HS400 speed mode should be the same as ITAPDLY
as HS200 timing after tuning is executed. Add the functionality
to save ITAPDLY from HS200 tuning and save as HS400 ITAPDLY.

Fixes: c964447ea3d6 ("mmc: am654_sdhci: Add support for input tap delay")
Signed-off-by: Judith Mendez <jm@ti.com>