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<title>u-boot.git/drivers, branch v2024.10-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>Merge patch series "Bug-fixes for a few boards"</title>
<updated>2024-08-05T18:17:02+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-08-05T18:15:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9efc554db8a6ab6e0c68d0f05fc273e5fb494e4e'/>
<id>9efc554db8a6ab6e0c68d0f05fc273e5fb494e4e</id>
<content type='text'>
Simon Glass &lt;sjg@chromium.org&gt; says:

This series includes fixes to get some rockchip and nvidia boards
working again. It also drops the broken Beaglebone Black config and
provides a devicetree fix for coral (x86).
</content>
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<pre>
Simon Glass &lt;sjg@chromium.org&gt; says:

This series includes fixes to get some rockchip and nvidia boards
working again. It also drops the broken Beaglebone Black config and
provides a devicetree fix for coral (x86).
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: Avoid #ifdefs in RK3399 SPL</title>
<updated>2024-08-05T18:17:01+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-08-01T12:47:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d63091137c8da5e1f3367c40ec607cd8918b8780'/>
<id>d63091137c8da5e1f3367c40ec607cd8918b8780</id>
<content type='text'>
The code here is confusing due to large blocks which are #ifdefed out.
Add a function phase_sdram_init() which returns whether SDRAM init
should happen in the current phase, using that as needed to control the
code flow.

This increases code size by about 500 bytes in SPL when the cache is on,
since it must call the rather large rockchip_sdram_size() function.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
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<pre>
The code here is confusing due to large blocks which are #ifdefed out.
Add a function phase_sdram_init() which returns whether SDRAM init
should happen in the current phase, using that as needed to control the
code flow.

This increases code size by about 500 bytes in SPL when the cache is on,
since it must call the rather large rockchip_sdram_size() function.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: Ensure memory size is available in RK3399 SPL</title>
<updated>2024-08-05T18:17:01+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-08-01T12:47:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0450e91c38d842593d2fcbdd7e1de8070e122efe'/>
<id>0450e91c38d842593d2fcbdd7e1de8070e122efe</id>
<content type='text'>
At present gd-&gt;ram_size is 0 in SPL, meaning that it is not possible to
enable the cache. Correct this by always populating the RAM size
correctly.

This increases code size by about 500 bytes in SPL, since it must call
the rather large rockchip_sdram_size() function.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Quentin Schulz &lt;quentin.schulz@cherry.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At present gd-&gt;ram_size is 0 in SPL, meaning that it is not possible to
enable the cache. Correct this by always populating the RAM size
correctly.

This increases code size by about 500 bytes in SPL, since it must call
the rather large rockchip_sdram_size() function.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Quentin Schulz &lt;quentin.schulz@cherry.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpu: imx: implement release_core callback</title>
<updated>2024-08-02T18:16:51+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2024-08-01T03:59:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8a73b5b680a849193287decf0ca3470fbd764e42'/>
<id>8a73b5b680a849193287decf0ca3470fbd764e42</id>
<content type='text'>
Release the secondary cores through the PSCI request.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Release the secondary cores through the PSCI request.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpu: imx: Add i.MX 8M series SoCs</title>
<updated>2024-08-02T18:16:51+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2024-08-01T03:59:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=01d94d006a2a9f02e76fb1660a6e8f64731bfe03'/>
<id>01d94d006a2a9f02e76fb1660a6e8f64731bfe03</id>
<content type='text'>
Add i.MX 8M Mini, Nano and Plus SoCs support.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add i.MX 8M Mini, Nano and Plus SoCs support.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpu: imx: removed the tail '\n' of the CPU description</title>
<updated>2024-08-02T18:16:51+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2024-08-01T03:59:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b7ed7418edb5378fb42a0e3744197b3d6a0383c8'/>
<id>b7ed7418edb5378fb42a0e3744197b3d6a0383c8</id>
<content type='text'>
Return CPU description string without newline character in the end.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Return CPU description string without newline character in the end.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpu: imx: fix the CPU type field width</title>
<updated>2024-08-02T18:16:51+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2024-08-01T03:59:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=37adedfb2116ed28b49c2581baf0f7eae69b97e1'/>
<id>37adedfb2116ed28b49c2581baf0f7eae69b97e1</id>
<content type='text'>
Increase one more bit to cover all CPU types. Otherwise it shows
wrong CPU info on some platforms, such as i.MX8M Plus:

    U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +0000)

    CPU:   NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C

    Model: NXP i.MX8MPlus LPDDR4 EVK board

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Increase one more bit to cover all CPU types. Otherwise it shows
wrong CPU info on some platforms, such as i.MX8M Plus:

    U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +0000)

    CPU:   NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C

    Model: NXP i.MX8MPlus LPDDR4 EVK board

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpu: imx: fix the CPU frequency in cpu_imx_get_info()</title>
<updated>2024-08-02T18:16:51+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2024-08-01T03:59:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dc86c11556c194a6a0beda82ee96549ad66d0aec'/>
<id>dc86c11556c194a6a0beda82ee96549ad66d0aec</id>
<content type='text'>
The cpu_freq stores the current CPU frequency in Hz.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Michael Trimarchi &lt;michael@amarulasolutions.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The cpu_freq stores the current CPU frequency in Hz.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Michael Trimarchi &lt;michael@amarulasolutions.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpu: sandbox: implement release_core callback</title>
<updated>2024-08-02T18:16:51+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2024-08-01T03:59:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3694edcabc4b62717cd71f64caacd4df2dbd5abd'/>
<id>3694edcabc4b62717cd71f64caacd4df2dbd5abd</id>
<content type='text'>
Add empty release CPU core function for testing.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add empty release CPU core function for testing.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpu: add release_core callback</title>
<updated>2024-08-02T18:16:51+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2024-08-01T03:59:47+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f2c306cd991a1c383de66ece1dd2301cd6b4b54b'/>
<id>f2c306cd991a1c383de66ece1dd2301cd6b4b54b</id>
<content type='text'>
Add a new callback release_core to the cpu_ops, which is used to
release a CPU core to run baremetal or RTOS application on a SoC
with multiple CPU cores.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a new callback release_core to the cpu_ops, which is used to
release a CPU core to run baremetal or RTOS application on a SoC
with multiple CPU cores.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
