u-boot.git/drivers, branch v2025.01

dma: ti: k3-udma: Fix BCDMA probe by adding check for MMR_RFLOW

2024-12-31T13:53:17+00:00

RFLOW config related MMR does not exist incase of BCDMA.
Add check to bypass the RFLOW MMR extraction.
Without this, the probe sequence fails checking for
the MMR_RFLOW region, which is valid only for packet based
DMA and obselete for BCDMA.

Fixes: 5abb694d6016 ("dma: ti: k3-udma: Add support for native configuration of chan/flow")
Signed-off-by: Prasanth Babu Mantena 
Tested-by: Jonathan Humphreys

mtd: spi-nor: Fix the spi_nor_read() when config SPI_STACKED_PARALLEL is enabled

2024-12-30T14:20:15+00:00

Update the spi_nor_read() function based on the config SPI_FLASH_BAR
and update the length and bank calculation by spliting the memory of
16MB size banks only when the address width is 3byte.
Fix the read issue for 4byte address width by passing the entire
length to the read function.

Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Venkatesh Yadav Abbarapu

crypto: typo volatge

2024-12-24T17:07:53+00:00

%s/volatge/voltage/g

Signed-off-by: Heinrich Schuchardt 
Acked-by: Peng Fan

net: rswitch: Do not register disabled ports as ethernet devices

2024-12-22T21:34:32+00:00

In case an rswitch port is described as disabled in DT, do not
register it as ethernet device in U-Boot. This way, such ports
cannot be accessed from U-Boot command line.

Signed-off-by: Marek Vasut

net: rswitch: Add missing cache invalidate of TX descriptor

2024-12-20T21:20:37+00:00

TFTP transfers of large files, for example 128 MiB, can sporadically
get stuck and the transfer slows down considerably.

This happens because the TX DMA descriptor in DRAM becomes out of sync
with the view of the TX DMA descriptor content from the CPU side, which
is viewed through the CPU caches. In order to guarantee these two views
are consistent, the cache over TX DMA descriptor that has possibly been
written by the rswitch hardware must first be invalidated, only then can
the descriptor be cleared and updated by the CPU, and finally the cache
over that area must be flushed back into DRAM to make sure the rswitch
hardware has consistent view of the updated descriptor content.

The very first invalidation operation was missing, which led to sporadic
corruption of the TX DMA descriptor. Fix it, add the missing invalidation
operation.

Reported-by: Enric Balletbo i Serra 
Signed-off-by: Marek Vasut 
Tested-by: Enric Balletbo i Serra

clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks

2024-12-20T21:20:37+00:00

Early revisions of the R-Car V4M Series Hardware User’s Manual
contained an incorrect formula for the CPU core clocks:

    ZCnφ = (PLL2VCO x 1/2) x mult/32

Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the
parent clock.

In Rev.0.70 of the documentation, the formula was corrected to:

    ZCnφ = (PLL2VCO x 1/4) x mult/32

As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2,
the use of CLK_PLL2_DIV2 is a recurring source of confusion.  Hence get
rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the
invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4
(and Gen3) SoCs.

Ported from Linux commit
92850bed9d4d ("clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks")

Reported-by: Vinh Nguyen 
Signed-off-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/0d2789cac2bf306145fe0bbf269c2da5942bb68f.1728377724.git.geert+renesas@glider.be
Signed-off-by: Marek Vasut

driver: clk: tegra: init basic clocks on probe

2024-12-16T23:07:39+00:00

In case DM drivers probe earlier than board clock setup is done
init of basic clocks should be done in CAR driver probe as well.
Add it to avoid possible clock related problems.

Acked-by: Thierry Reding 
Signed-off-by: Svyatoslav Ryhel

driver: clk: tegra: partially support PLL clocks

2024-12-16T23:07:39+00:00

Return PLL id into struct clk if PLL is parsed from device
tree instead of throwing an error. Allow requesting PLL
clock rate via get_rate op.

Signed-off-by: Svyatoslav Ryhel

mmc: Fix potential timer value truncation

2024-12-16T02:24:42+00:00

On 64bit systems the timer value might be truncated to a 32bit value
causing malfunctions. For example on ARM the timer might start from 0
again only after a cold reset. The 32bit overflow occurs after a bit
more than 49 days (1000 Hz counter) so booting after that time may lead
to a surprise because the board might become stuck requiring a cold
reset.

Signed-off-by: Ronald Wahl 
Cc: Peng Fan 
Cc: Jaehoon Chung 
Reviewed-by: Jaehoon Chung

clk: mpc83xx: Fix typo in "Coherent System Bus"

2024-12-15T01:03:52+00:00

Cosmetic change.

Signed-off-by: J. Neuschäfer