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<title>u-boot.git/drivers, branch v2025.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>Merge patch series "Fix IOVA allocation in Apple dart iommu after global LMB mem map changes"</title>
<updated>2024-11-11T15:11:55+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-11-11T13:26:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=48fd7e9699f8799690196c76869d59c1e5b2e9a6'/>
<id>48fd7e9699f8799690196c76869d59c1e5b2e9a6</id>
<content type='text'>
Janne Grunau &lt;j@jannau.net&gt; says:

The changes in "Make LMB memory map global and persistent" [1] break
mapping DMA memory in the USB xHCI driver when using the apple_dart
iommu present on Apple silicon systems.

The IOVA space used by the u-boot driver (low 4GB) and physical memory
do not overlap. The physical memory on this systems starts depending on
the SoC either at 0x10_0000_0000 or 0x100_0000_0000. It make no sense to
manage these distinct regions in a single LMB map. In addition every
device has its own iommu and IO address space so sharing a single memory
map between all iommu instances is not necessary.

To fix this issue restore the used subset (add, alloc and free) of the
previous pointer based LMB interface with "io_" as prefix.

To ensure that low level lmb functions do not use the global LMB
variable reorder lib/lmb.c so that the variable is not visible.

Tested with patches from my "Fix device removal order for Apple dart
iommu" series [2] to fix a separate issue.

The cosmetic commit has two checkpatch warnings in existing code which I
ignored.

[1] https://lore.kernel.org/u-boot/20240826115940.3233167-1-sughosh.ganu@linaro.org/
[2] https://lore.kernel.org/u-boot/20241031-iommu_apple_dart_ordering-v1-0-8a6877946d6b@jannau.net/

Link: https://lore.kernel.org/r/20241111-io_lmb_apple_dart_iommu-v3-0-32c05da51d72@jannau.net
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
Janne Grunau &lt;j@jannau.net&gt; says:

The changes in "Make LMB memory map global and persistent" [1] break
mapping DMA memory in the USB xHCI driver when using the apple_dart
iommu present on Apple silicon systems.

The IOVA space used by the u-boot driver (low 4GB) and physical memory
do not overlap. The physical memory on this systems starts depending on
the SoC either at 0x10_0000_0000 or 0x100_0000_0000. It make no sense to
manage these distinct regions in a single LMB map. In addition every
device has its own iommu and IO address space so sharing a single memory
map between all iommu instances is not necessary.

To fix this issue restore the used subset (add, alloc and free) of the
previous pointer based LMB interface with "io_" as prefix.

To ensure that low level lmb functions do not use the global LMB
variable reorder lib/lmb.c so that the variable is not visible.

Tested with patches from my "Fix device removal order for Apple dart
iommu" series [2] to fix a separate issue.

The cosmetic commit has two checkpatch warnings in existing code which I
ignored.

[1] https://lore.kernel.org/u-boot/20240826115940.3233167-1-sughosh.ganu@linaro.org/
[2] https://lore.kernel.org/u-boot/20241031-iommu_apple_dart_ordering-v1-0-8a6877946d6b@jannau.net/

Link: https://lore.kernel.org/r/20241111-io_lmb_apple_dart_iommu-v3-0-32c05da51d72@jannau.net
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>iommu: apple: Manage IOVA separately from global LMB mem map</title>
<updated>2024-11-11T13:26:44+00:00</updated>
<author>
<name>Janne Grunau</name>
<email>j@jannau.net</email>
</author>
<published>2024-11-11T06:56:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f642f344348558e05902175e7517c7a12f2c5562'/>
<id>f642f344348558e05902175e7517c7a12f2c5562</id>
<content type='text'>
There is no overlap between the IOVA space managed by the iommu (here
the 32-bit address space) and physical RAM on Apple silicon systems. The
RAM starts at 0x10_0000_0000 or 0x100_0000_0000 so it's not possible to
manage the IOVA with the global memory LMB and use 1:1 translation.
In addition each device has its own iommu and does not need to share the
address space with all other devices. This should not be problem for
u-boot's limited use and hardware support.
Restore the private per instance LMB IOVA map.

Fixes: ed17a33fed2 ("lmb: make LMB memory map persistent and global")
Signed-off-by: Janne Grunau &lt;j@jannau.net&gt;
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<pre>
There is no overlap between the IOVA space managed by the iommu (here
the 32-bit address space) and physical RAM on Apple silicon systems. The
RAM starts at 0x10_0000_0000 or 0x100_0000_0000 so it's not possible to
manage the IOVA with the global memory LMB and use 1:1 translation.
In addition each device has its own iommu and does not need to share the
address space with all other devices. This should not be problem for
u-boot's limited use and hardware support.
Restore the private per instance LMB IOVA map.

Fixes: ed17a33fed2 ("lmb: make LMB memory map persistent and global")
Signed-off-by: Janne Grunau &lt;j@jannau.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-rockchip-20241111' of https://source.denx.de/u-boot/custodians/u-boot-rockchip</title>
<updated>2024-11-11T13:25:25+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-11-11T13:25:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fdcf06d58d94c40eb02a9c034af613cee08eb3f2'/>
<id>fdcf06d58d94c40eb02a9c034af613cee08eb3f2</id>
<content type='text'>
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/23280

- Add board:
        rk3328: FriendlyElec NanoPi R2S Plus
        rk3568: Qnap TS433
        rk3588: Cool Pi CM5 GenBook
- Move rk3399_force_power_on_reset to TPL for puma board;
</content>
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<pre>
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/23280

- Add board:
        rk3328: FriendlyElec NanoPi R2S Plus
        rk3568: Qnap TS433
        rk3588: Cool Pi CM5 GenBook
- Move rk3399_force_power_on_reset to TPL for puma board;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: rockchip: allow to build for TPL</title>
<updated>2024-11-11T07:14:14+00:00</updated>
<author>
<name>Quentin Schulz</name>
<email>quentin.schulz@cherry.de</email>
</author>
<published>2024-11-06T11:29:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5bc65f5cab2369e0053d19df356b4bcb31150409'/>
<id>5bc65f5cab2369e0053d19df356b4bcb31150409</id>
<content type='text'>
A later commit will make use of the pinctrl driver in TPL so let's add
the ability to build the Rockchip pinctrl driver in TPL.

Reviewed-by: Paul Kocialkowski &lt;paulk@sys-base.io&gt;
Signed-off-by: Quentin Schulz &lt;quentin.schulz@cherry.de&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
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<pre>
A later commit will make use of the pinctrl driver in TPL so let's add
the ability to build the Rockchip pinctrl driver in TPL.

Reviewed-by: Paul Kocialkowski &lt;paulk@sys-base.io&gt;
Signed-off-by: Quentin Schulz &lt;quentin.schulz@cherry.de&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mtd: spi-nor: Fix integer overflow in stacked memories support</title>
<updated>2024-11-11T02:21:07+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-11-02T23:57:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=24b28ffc40d464696b909ca5a4e860e09343397b'/>
<id>24b28ffc40d464696b909ca5a4e860e09343397b</id>
<content type='text'>
The 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
adds new SPI bus flags, but also introduces a completely new set of
SPI bus flags in another location. The existing flags field is type
u8, while the new separate flags are BIT(8) and higher. Use of those
new flags triggers integer overflow.

Drop the newly introduced flags which were never used anywhere in the
code. Move the one remaining flag which was used in the correct place
and change it from BIT(8) to BIT(6) so it fits the u8 flags.

Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Addresses-Coverity-ID: 510804 Extra high-order bits
Reported-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
Reviewed-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
</content>
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<pre>
The 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
adds new SPI bus flags, but also introduces a completely new set of
SPI bus flags in another location. The existing flags field is type
u8, while the new separate flags are BIT(8) and higher. Use of those
new flags triggers integer overflow.

Drop the newly introduced flags which were never used anywhere in the
code. Move the one remaining flag which was used in the correct place
and change it from BIT(8) to BIT(6) so it fits the u8 flags.

Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Addresses-Coverity-ID: 510804 Extra high-order bits
Reported-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
Reviewed-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>driver: sifive ccache: enable TRUNKCLOCKGATE and REGIONCLOCKGATE</title>
<updated>2024-11-06T10:56:51+00:00</updated>
<author>
<name>Nick Hu</name>
<email>nick.hu@sifive.com</email>
</author>
<published>2024-10-30T07:58:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=33ddfc059ee310640ef33c1a92dddaa1af84324d'/>
<id>33ddfc059ee310640ef33c1a92dddaa1af84324d</id>
<content type='text'>
Enable the clock gating bit of ccache when the platform has the ccache0.

Signed-off-by: Nick Hu &lt;nick.hu@sifive.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
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<pre>
Enable the clock gating bit of ccache when the platform has the ccache0.

Signed-off-by: Nick Hu &lt;nick.hu@sifive.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>bios_emulator: fix first argument of pci_{read,write}_config_* function calls</title>
<updated>2024-11-05T00:01:58+00:00</updated>
<author>
<name>Yuri Zaporozhets</name>
<email>yuriz@vodafonemail.de</email>
</author>
<published>2024-10-30T19:38:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=56accc56b9aab87ef4809ccc588e1257969cd271'/>
<id>56accc56b9aab87ef4809ccc588e1257969cd271</id>
<content type='text'>
When compiling for riscv64, a bunch of warning is produced for the file
drivers/bios_emulator/besys.c. This patch fixes a portion of those warnings,
caused by incorrect first argument to pci_{read,write}_config_* functions.

Signed-off-by: Yuri Zaporozhets &lt;yuriz@qrv-systems.net&gt;
</content>
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<pre>
When compiling for riscv64, a bunch of warning is produced for the file
drivers/bios_emulator/besys.c. This patch fixes a portion of those warnings,
caused by incorrect first argument to pci_{read,write}_config_* functions.

Signed-off-by: Yuri Zaporozhets &lt;yuriz@qrv-systems.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers/video/vesa: use MTRRs only on x86</title>
<updated>2024-11-04T22:41:38+00:00</updated>
<author>
<name>Yuri Zaporozhets</name>
<email>yuriz@vodafonemail.de</email>
</author>
<published>2024-10-30T13:17:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7837e273df58cafb405a640364da4755b6d35c89'/>
<id>7837e273df58cafb405a640364da4755b6d35c89</id>
<content type='text'>
MTRR functionality is available only on x86, so this driver cannot be compiled
on other architectures. Fix this with preprocessor directives.

Signed-off-by: Yuri Zaporozhets &lt;yuriz@qrv-systems.net&gt;
</content>
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<pre>
MTRR functionality is available only on x86, so this driver cannot be compiled
on other architectures. Fix this with preprocessor directives.

Signed-off-by: Yuri Zaporozhets &lt;yuriz@qrv-systems.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>bios_emulator: define the comment symbol for RISC-V assembler too</title>
<updated>2024-11-04T22:41:38+00:00</updated>
<author>
<name>Yuri Zaporozhets</name>
<email>yuriz@vodafonemail.de</email>
</author>
<published>2024-10-30T13:00:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d84e3d2630f9db9484ee8609e5d5e992fc5c5260'/>
<id>d84e3d2630f9db9484ee8609e5d5e992fc5c5260</id>
<content type='text'>
The bios_emulator driver cannot be compiled for RISC-V because the x86emu.h
header file doesn't define the comment symbol ("#") for the assembler.
With this patch, use the same symbol as for e.g. x86.

Signed-off-by: Yuri Zaporozhets &lt;yuriz@qrv-systems.net&gt;
</content>
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<pre>
The bios_emulator driver cannot be compiled for RISC-V because the x86emu.h
header file doesn't define the comment symbol ("#") for the assembler.
With this patch, use the same symbol as for e.g. x86.

Signed-off-by: Yuri Zaporozhets &lt;yuriz@qrv-systems.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: core: Add a function to see if a device exists</title>
<updated>2024-11-04T03:27:12+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-10-19T15:21:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=79b3e9d25b3f96fdf66f9d7dc6a14fdce9a15f93'/>
<id>79b3e9d25b3f96fdf66f9d7dc6a14fdce9a15f93</id>
<content type='text'>
All the uclass functions for finding a device end up creating a uclass
if it doesn't exist. Add a function which instead returns NULL in this
case.

This is useful when in the 'unbind' path, since we don't want to undo
any unbinding which has already happened.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
All the uclass functions for finding a device end up creating a uclass
if it doesn't exist. Add a function which instead returns NULL in this
case.

This is useful when in the 'unbind' path, since we don't want to undo
any unbinding which has already happened.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
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